From patchwork Mon Jun 2 09:09:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4280671 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3C7079F1D6 for ; Mon, 2 Jun 2014 09:11:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E6EB203AB for ; Mon, 2 Jun 2014 09:11:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 87172202EB for ; Mon, 2 Jun 2014 09:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753464AbaFBJJc (ORCPT ); Mon, 2 Jun 2014 05:09:32 -0400 Received: from mail-wi0-f177.google.com ([209.85.212.177]:37515 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753104AbaFBJJ2 (ORCPT ); Mon, 2 Jun 2014 05:09:28 -0400 Received: by mail-wi0-f177.google.com with SMTP id f8so4152195wiw.10 for ; Mon, 02 Jun 2014 02:09:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UyxV+lYVk81gU27EU0duqimd1MNkwk/kz3gEKtM1Y7k=; b=LlXw9zOlDxtsTpObEi0g55cly9WFX9t+69vPG4FjWZWVU6gYcY2Dr8tPfVD+NOitrQ Tzb88GKaErJUmAj6xWgO12MJy90LQAyWMX6blw6DB6Z7BGKC+WFGTTv0YzQIOP03Eh1o xPvyRzntG8l4/jrxd/RPFUg20pYGqrZv2WLrR0lFsL6zUEL5UVpz96KnwBtXgscd8VLP ksUA38slEn2lxN1C8yCIBVLdaJWqEIZLaIzoM3hMnsOhfF+A+HvSFE0jEUoLCTPjde/D B/YM9Jagfrp5KRBBCK8nKZbJnHXsE7SIKRrlYIcrSs13iuCYf4QN1raWCI4vi4JDt+hP eZpQ== X-Gm-Message-State: ALoCoQkreWYmLj9eEEXBG3VdohM7UpIzeRpcOxPVjH7oGWhvob+GDN2RkyqwJOHs/GZDEXYc3dwS X-Received: by 10.180.82.133 with SMTP id i5mr20604580wiy.50.1401700166777; Mon, 02 Jun 2014 02:09:26 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-149-12-106.as13285.net. [78.149.12.106]) by mx.google.com with ESMTPSA id lo18sm30864492wic.1.2014.06.02.02.09.25 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Jun 2014 02:09:25 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v6 06/12] mmc: mmci: add 8bit bus support in variant data Date: Mon, 2 Jun 2014 10:09:23 +0100 Message-Id: <1401700163-11670-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401699818-11329-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1401699818-11329-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index ad7e538..fa3ad83 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @clkreg_8bit_bus_enable: enable value for 8 bit bus * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -72,6 +73,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int clkreg_8bit_bus_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -113,6 +115,7 @@ static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 16, .sdio = true, .pwrreg_powerup = MCI_PWR_ON, @@ -139,6 +142,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, @@ -154,6 +158,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -305,7 +310,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) clk |= MCI_ST_UX500_NEG_EDGE;