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[24.8.37.141]) by mx.google.com with ESMTPSA id n8sm2163342pdm.22.2014.08.07.21.05.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Aug 2014 21:05:49 -0700 (PDT) From: Lina Iyer To: daniel.lezcano@linaro.org, khilman@linaro.org, amit.kucheria@linaro.org, sboyd@codeaurora.org, davidb@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org Cc: msivasub@codeaurora.org, bryanh@codeaurora.org, Lina Iyer Subject: [RFC] [PATCH 10/13] qcom: platsmp: Enable deeper idle states for hotplug Date: Thu, 7 Aug 2014 22:05:19 -0600 Message-Id: <1407470722-23015-11-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407470722-23015-1-git-send-email-lina.iyer@linaro.org> References: <1407470722-23015-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allow cpu and system deeper sleep modes when a cpu is hotplugged. Calling wfi() executes architectural clock gating supported by the ARM core, while this is useful, it does not save leakage power and does not help in reducing power in the peripheral logic surrounding the cpu. QCOM platforms have a sub-system power manager to control the logic around the core. Pass the hotplug call over to SoC idle interface driver to allow for the core and the peripheral logic to enter low power when hotplugged. Signed-off-by: Lina Iyer --- arch/arm/mach-qcom/platsmp.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index d690856..c40f220 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -20,7 +20,8 @@ #include -#include "scm-boot.h" +#include +#include #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0 #define SCSS_CPU1CORE_RESET 0x2d80 @@ -51,12 +52,30 @@ static DEFINE_SPINLOCK(boot_lock); #ifdef CONFIG_HOTPLUG_CPU static void __ref qcom_cpu_die(unsigned int cpu) { +#if defined CONFIG_QCOM_PM + for (;;) + msm_pm_cpu_hotplug_enter(cpu); +#else wfi(); +#endif +} + +static int __ref qcom_cpu_kill(unsigned int cpu) +{ + int ret = 0; + +#if defined CONFIG_QCOM_PM + ret = msm_pm_wait_cpu_shutdown(cpu) ? 0 : 1; +#endif + return ret; } + #endif static void qcom_secondary_init(unsigned int cpu) { + msm_pm_secondary_startup(cpu); + /* * Synchronise with the boot thread. */ @@ -373,6 +392,7 @@ static struct smp_operations qcom_smp_kpssv2_ops __initdata = { .smp_boot_secondary = kpssv2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, + .cpu_kill = qcom_cpu_kill, #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);