From patchwork Fri Jan 16 14:48:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 5649111 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A8562C058D for ; Fri, 16 Jan 2015 14:50:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D3837201F4 for ; Fri, 16 Jan 2015 14:50:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AF5342010F for ; Fri, 16 Jan 2015 14:50:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756373AbbAPOss (ORCPT ); Fri, 16 Jan 2015 09:48:48 -0500 Received: from smtp.codeaurora.org ([198.145.11.231]:49665 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756339AbbAPOsq (ORCPT ); Fri, 16 Jan 2015 09:48:46 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 7E439141044; Fri, 16 Jan 2015 14:48:45 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 63974141041; Fri, 16 Jan 2015 14:48:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (unknown [202.46.23.60]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E74FE14103D; Fri, 16 Jan 2015 14:48:43 +0000 (UTC) From: Archit Taneja To: linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, agross@codeaurora.org, galak@codeaurora.org, Archit Taneja , devicetree@vger.kernel.org Subject: [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller Date: Fri, 16 Jan 2015 20:18:20 +0530 Message-Id: <1421419702-17812-4-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1421419702-17812-1-git-send-email-architt@codeaurora.org> References: <1421419702-17812-1-git-send-email-architt@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja --- .../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt new file mode 100644 index 0000000..e24c77a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -0,0 +1,48 @@ +* Qualcomm NAND controller + +Required properties: +- compatible: should be "qcom,ebi2-nand" for IPQ806x +- reg: MMIO address range +- clocks: must contain core clock and always on clock +- clock-names: must contain "core" for the core clock and "aon" for the + always on clock +- dmas: DMA specifier, consisting of a phandle to the ADM DMA + controller node and the channel number to be used for + NAND. Refer to dma.txt and qcom_adm.txt for more details +- dma-names: must be "rxtx" +- qcom,cmd-crci: must contain the ADM command type CRCI block instance + number specified for the NAND controller on the given + platform +- qcom,data-crci: must contain the ADM data type CRCI block instance + number specified for the NAND controller on the given + platform + +Optional properties: +- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen + as default + +- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8 + bits. If not present, 4 is chosen as default + +The device tree may optionally contain sub-nodes describing partitions of the +address space. See partition.txt for more detail. + +Example: + +nand@0x1ac00000 { + compatible = "qcom,ebi2-nandc"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + partition@0 { + ... + }; +};