From patchwork Thu Mar 19 08:02:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6047321 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 344129F440 for ; Thu, 19 Mar 2015 08:03:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3D38F2051D for ; Thu, 19 Mar 2015 08:03:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3E2B82051C for ; Thu, 19 Mar 2015 08:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753935AbbCSIDX (ORCPT ); Thu, 19 Mar 2015 04:03:23 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:47756 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753865AbbCSIDS (ORCPT ); Thu, 19 Mar 2015 04:03:18 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 3F63B13FCE6; Thu, 19 Mar 2015 08:03:17 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 2D79413FD1E; Thu, 19 Mar 2015 08:03:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CC72413FCE6; Thu, 19 Mar 2015 08:03:13 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@linaro.org Cc: linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, linux-arm-kernel@lists.infradead.org, svarbanov@mm-sol.com, Rajendra Nayak Subject: [PATCH v2 2/6] clk: qcom: gdsc: Prepare common clk probe to register gdscs Date: Thu, 19 Mar 2015 13:32:21 +0530 Message-Id: <1426752145-4365-3-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1426752145-4365-1-git-send-email-rnayak@codeaurora.org> References: <1426752145-4365-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/common.c | 14 +++++++++++++- drivers/clk/qcom/common.h | 2 ++ drivers/clk/qcom/gdsc.c | 34 +++++++++++++++++++++++++++++++++- drivers/clk/qcom/gdsc.h | 9 ++++++++- 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index a946b48..cc9f56f 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -21,6 +21,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" +#include "gdsc.h" struct qcom_cc { struct qcom_reset_controller reset; @@ -125,8 +126,18 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = reset_controller_register(&reset->rcdev); if (ret) - of_clk_del_provider(dev->of_node); + goto err_reset; + ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap); + if (ret) + goto err_pd; + + return 0; +err_pd: + dev_err(dev, "Failed to register power domains\n"); + reset_controller_unregister(&reset->rcdev); +err_reset: + of_clk_del_provider(dev->of_node); return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); @@ -145,6 +156,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe); void qcom_cc_remove(struct platform_device *pdev) { + of_genpd_del_provider(pdev->dev.of_node); of_clk_del_provider(pdev->dev.of_node); reset_controller_unregister(platform_get_drvdata(pdev)); } diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index b3d7e57..480fdbe 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -27,6 +27,8 @@ struct qcom_cc_desc { size_t num_clks; const struct qcom_reset_map *resets; size_t num_resets; + struct gdsc **gdscs; + size_t num_gdscs; }; extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 4c89312..7de9a00 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "gdsc.h" #define PWR_ON_MASK BIT(31) @@ -100,7 +101,7 @@ static int gdsc_disable(struct generic_pm_domain *domain) return gdsc_toggle_logic(sc, false); } -int gdsc_init(struct gdsc *sc) +static int gdsc_init(struct gdsc *sc) { u32 mask, val; int on, ret; @@ -127,3 +128,34 @@ int gdsc_init(struct gdsc *sc) return 0; } + +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num, + struct regmap *regmap) +{ + int i, ret; + struct genpd_onecell_data *data; + + if (!num || !scs || !dev || !dev->of_node) + return 0; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->domains = devm_kzalloc(dev, sizeof(*data->domains) * num, + GFP_KERNEL); + if (!data->domains) + return -ENOMEM; + + data->num_domains = num; + for (i = 0; i < num; i++) { + if (!scs[i]) + continue; + scs[i]->regmap = regmap; + ret = gdsc_init(scs[i]); + if (ret) + return ret; + data->domains[i] = &scs[i]->pd; + } + return of_genpd_add_provider_onecell(dev->of_node, data); +} diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index ac6a2d5..14de304 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -32,5 +32,12 @@ struct gdsc { #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) -int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap); +#ifdef CONFIG_QCOM_GDSC +int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *); +#else +int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct regmap *r) +{ + return 0; +} +#endif /* CONFIG_QCOM_GDSC */ #endif /* __QCOM_GDSC_H__ */