From patchwork Thu Apr 30 17:17:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 6306121 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BCE829F373 for ; Thu, 30 Apr 2015 17:17:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B3565201B9 for ; Thu, 30 Apr 2015 17:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C75120219 for ; Thu, 30 Apr 2015 17:17:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752417AbbD3RRe (ORCPT ); Thu, 30 Apr 2015 13:17:34 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:34581 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752400AbbD3RRW (ORCPT ); Thu, 30 Apr 2015 13:17:22 -0400 Received: by wicmx19 with SMTP id mx19so17951434wic.1 for ; Thu, 30 Apr 2015 10:17:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K0rSdZbkh568zTJAoAbusq/kojQbbD4MfXSFAFrhim0=; b=I9YXmf/JtXly7D1IbwdfmxxBVuRKVVlfeQDpQqrKkGnB8MVanRdIbp+Xpo/+qLrgx7 KY6vuuOJi3fQxJS/DyB74E0Q+xb4EJRVUUZlYtAbR1c9fOgK1OgMFsZJKlO6FOJouGI1 FRFngnN62G6WPPzDYSkIOw9WoW+3d8HW0FQOwj0rYREAESjv41VhESHzp5x+c21VQ5yN /jD2xF9XlYkUBxYZHE1Uzg3rmSvQrxxRsWbmD0/YbtpMYFiAVGqzUaKFBcgMF7337F5k azKguTjqZSA2Eh6Z6b+bAE2RjWgVwuLcBMqsl4SyOJlqw/iDt0+VChcbPUO/1hS2n2Cr 4YGw== X-Gm-Message-State: ALoCoQkYWiQZG1FgK8+RFWzvDel5TP8X/cU65wpXvrhcHr+lZcQndQT/1djZ/1kFs3dn0jfT7yk7 X-Received: by 10.180.98.230 with SMTP id el6mr7452312wib.16.1430414240575; Thu, 30 Apr 2015 10:17:20 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-2-98-219-188.as13285.net. [2.98.219.188]) by mx.google.com with ESMTPSA id n3sm3576580wix.1.2015.04.30.10.17.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 10:17:19 -0700 (PDT) From: Srinivas Kandagatla To: Patrick Lai , Mark Brown Cc: Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Banajit Goswami , Kenneth Westfield , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [RFC PATCH 06/14] ASoC: qcom: support bitclk and osrclk per i2s port Date: Thu, 30 Apr 2015 18:17:17 +0100 Message-Id: <1430414237-11126-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430414148-10869-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1430414148-10869-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to allow bitclk and osrclk per i2s dai port. on APQ8016 there are 4 i2s ports each one has its own bit clks. Without this patch its not possible to support multiple i2s ports in the lpass driver. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass-cpu.c | 53 ++++++++++++++++++++++++++++++---------------- sound/soc/qcom/lpass.h | 5 +++-- 2 files changed, 38 insertions(+), 20 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 7aca253..66d068b 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -33,7 +33,7 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_set_rate(drvdata->mi2s_osr_clk, freq); + ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->id], freq); if (ret) dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n", __func__, freq, ret); @@ -47,18 +47,18 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk); + ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", __func__, ret); return ret; } - ret = clk_prepare_enable(drvdata->mi2s_bit_clk); + ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n", __func__, ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk); + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); return ret; } @@ -70,8 +70,8 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); - clk_disable_unprepare(drvdata->mi2s_bit_clk); - clk_disable_unprepare(drvdata->mi2s_osr_clk); + clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->id]); + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, @@ -146,7 +146,7 @@ static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, return ret; } - ret = clk_set_rate(drvdata->mi2s_bit_clk, rate * bitwidth * 2); + ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->id], rate * bitwidth * 2); if (ret) { dev_err(dai->dev, "%s() error setting mi2s bitclk to %u: %d\n", __func__, rate * bitwidth * 2, ret); @@ -351,7 +351,8 @@ int lpass_cpu_platform_probe(struct platform_device *pdev) struct lpass_variant *variant; struct device *dev = &pdev->dev; const struct of_device_id *match; - int ret; + char clk_name[16]; + int ret, i; dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); if (dsp_of_node) { @@ -397,18 +398,34 @@ int lpass_cpu_platform_probe(struct platform_device *pdev) if (variant->init) variant->init(pdev); - drvdata->mi2s_osr_clk = devm_clk_get(&pdev->dev, "mi2s-osr-clk"); - if (IS_ERR(drvdata->mi2s_osr_clk)) { - dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_osr_clk)); - return PTR_ERR(drvdata->mi2s_osr_clk); + for (i = 0; i < variant->num_dai; i++) { + if (variant->num_dai > 1) + sprintf(clk_name, "mi2s-osr-clk%d", i); + else + sprintf(clk_name, "mi2s-osr-clk"); + + drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(drvdata->mi2s_osr_clk[i])) { + dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", + __func__, PTR_ERR(drvdata->mi2s_osr_clk[i])); + return PTR_ERR(drvdata->mi2s_osr_clk[i]); + } } - drvdata->mi2s_bit_clk = devm_clk_get(&pdev->dev, "mi2s-bit-clk"); - if (IS_ERR(drvdata->mi2s_bit_clk)) { - dev_err(&pdev->dev, "%s() error getting mi2s-bit-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_bit_clk)); - return PTR_ERR(drvdata->mi2s_bit_clk); + for (i = 0; i < variant->num_dai; i++) { + + if (variant->num_dai > 1) + sprintf(clk_name, "mi2s-bit-clk%d", i); + else + sprintf(clk_name, "mi2s-bit-clk"); + + drvdata->mi2s_bit_clk[i] = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(drvdata->mi2s_bit_clk[i])) { + dev_err(&pdev->dev, + "%s() error getting mi2s-bit-clk: %ld\n", + __func__, PTR_ERR(drvdata->mi2s_bit_clk[i])); + return PTR_ERR(drvdata->mi2s_bit_clk[i]); + } } drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk"); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 80f4b1c..6ce2a51 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -22,6 +22,7 @@ #include #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 +#define LPASS_MAX_MI2S_PORTS (4) /* Both the CPU DAI and platform drivers will access this data */ struct lpass_data { @@ -30,10 +31,10 @@ struct lpass_data { struct clk *ahbix_clk; /* MI2S system clock */ - struct clk *mi2s_osr_clk; + struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; /* MI2S bit clock (derived from system clock by a divider */ - struct clk *mi2s_bit_clk; + struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; /* low-power audio interface (LPAIF) registers */ void __iomem *lpaif;