From patchwork Thu Apr 30 17:17:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 6306311 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0596FBEEE1 for ; Thu, 30 Apr 2015 17:19:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 28BBE201F5 for ; Thu, 30 Apr 2015 17:19:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 179252018E for ; Thu, 30 Apr 2015 17:19:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752520AbbD3RRc (ORCPT ); Thu, 30 Apr 2015 13:17:32 -0400 Received: from mail-wg0-f52.google.com ([74.125.82.52]:35753 "EHLO mail-wg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752362AbbD3RR3 (ORCPT ); Thu, 30 Apr 2015 13:17:29 -0400 Received: by wgyo15 with SMTP id o15so69818435wgy.2 for ; Thu, 30 Apr 2015 10:17:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=89IMZrIiF7RG0Se8mtEWj2OfVbpW4+BdAJDC4wZOLM0=; b=VK5jRZZ75CPO40BND5qlYMy2O+M/Xy9fD9nAB9Nh34zqoKGJkqkd46BxbCqCcKyjBv KCjsM8Pjk0pYT1D0oLicriYHifgKvPZrANnLehs0x3xEtEr7vuH8YMWLPZfom0iEY2u+ gVwoJCTEDA0KlVDu0rQRttOoZHa7/K4sP+UNYFr0Yaf+P41m8xCCWuvgO0Ik95X490hK bloxINIlyHf2iMIGrE/B9/vnhHIOFly45pd9LRt6mLa9OUdC67zJRDw0sHcbhqfvbfI2 j0CQaEXythFDnP4tp6kUOc9RRcvE5Eq4AIA9K6BaYH2sCwwFtuF87sjo6DmU2T6fsZm2 YSvA== X-Gm-Message-State: ALoCoQm+eZ3RExW+Z4QIMuA03PhMN0WYc1UR7/gZm8uTg6EtEkrDZqR6TvybP9kv7kUpScgB5iu9 X-Received: by 10.180.7.133 with SMTP id j5mr7519458wia.84.1430414248298; Thu, 30 Apr 2015 10:17:28 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-2-98-219-188.as13285.net. [2.98.219.188]) by mx.google.com with ESMTPSA id l3sm3287088wik.16.2015.04.30.10.17.26 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 10:17:27 -0700 (PDT) From: Srinivas Kandagatla To: Patrick Lai , Mark Brown Cc: Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Banajit Goswami , Kenneth Westfield , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [RFC PATCH 07/14] ASoC: qcom: add no osr clk flag to lpass variant Date: Thu, 30 Apr 2015 18:17:24 +0100 Message-Id: <1430414244-11168-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430414148-10869-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1430414148-10869-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some LPASS integrations like on APQ8016 do not have OSR clk, so adding no osr clk bit would allow such integrations to use lpass driver. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass-cpu.c | 49 +++++++++++++++++++++++++++++----------------- sound/soc/qcom/lpass.h | 2 ++ 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 66d068b..17ad20d 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -33,6 +33,9 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; + if (drvdata->variant->no_osr_clk) + return 0; + ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->id], freq); if (ret) dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n", @@ -47,18 +50,21 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->id]); - if (ret) { - dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", - __func__, ret); - return ret; + if (!drvdata->variant->no_osr_clk) { + ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->id]); + if (ret) { + dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", + __func__, ret); + return ret; + } } ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n", __func__, ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); + if (!drvdata->variant->no_osr_clk) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); return ret; } @@ -71,7 +77,9 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->id]); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); + + if (!drvdata->variant->no_osr_clk) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->id]); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, @@ -398,17 +406,22 @@ int lpass_cpu_platform_probe(struct platform_device *pdev) if (variant->init) variant->init(pdev); - for (i = 0; i < variant->num_dai; i++) { - if (variant->num_dai > 1) - sprintf(clk_name, "mi2s-osr-clk%d", i); - else - sprintf(clk_name, "mi2s-osr-clk"); - - drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, clk_name); - if (IS_ERR(drvdata->mi2s_osr_clk[i])) { - dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_osr_clk[i])); - return PTR_ERR(drvdata->mi2s_osr_clk[i]); + if (!variant->no_osr_clk) { + for (i = 0; i < variant->num_dai; i++) { + if (variant->num_dai > 1) + sprintf(clk_name, "mi2s-osr-clk%d", i); + else + sprintf(clk_name, "mi2s-osr-clk"); + + drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, + clk_name); + if (IS_ERR(drvdata->mi2s_osr_clk[i])) { + dev_err(&pdev->dev, + "%s() error getting mi2s-osr-clk: %ld\n", + __func__, + PTR_ERR(drvdata->mi2s_osr_clk[i])); + return PTR_ERR(drvdata->mi2s_osr_clk[i]); + } } } diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 6ce2a51..301f784 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -61,6 +61,8 @@ struct lpass_variant { u32 rdma_reg_stride; u32 rdma_channels; + /* OCR clock is not present in SOCs like APQ8016 */ + bool no_osr_clk; /* SOC specific intialization like clocks */ int (*init)(struct platform_device *pdev); int (*exit)(struct platform_device *pdev);