From patchwork Wed May 13 12:02:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 6396271 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F14C9BEEE1 for ; Wed, 13 May 2015 12:02:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1DE3F2041A for ; Wed, 13 May 2015 12:02:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F34A4203EB for ; Wed, 13 May 2015 12:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933915AbbEMMCg (ORCPT ); Wed, 13 May 2015 08:02:36 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:38831 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933998AbbEMMCf (ORCPT ); Wed, 13 May 2015 08:02:35 -0400 Received: by wicnf17 with SMTP id nf17so52792590wic.1 for ; Wed, 13 May 2015 05:02:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=heD44tJ4zKqBRCiEtFScLZqsLX9ZOsF7WB7LUgQea4Y=; b=j0r/MVNE1N20wBOzWk/8ArrZ0CgmK9izkrU4O4YDYAopU1EViL3ZJuqBRXH8Pb56ho Bip8/UC6rS90B2wfJfJ1dhpB5BUxNG3FdyRK+nP2CdYBZ9h5xC1rZ9BJjiedpX9kqTMl qVPsOpcSVXUHYi2xYt/jHbcUAIgTA0BsDj5CFbv4AgR3Kc7efyEg2178Ad9tfbsNKFa+ z4fjBBf9NXdeYhMCI73AafQs32ecXhsAIF4wPiuACxucHKPDgN2h77faQ0P65cFQScrG w98mWrR29dUej4trzJBbeO3sojPHgCZ1WsQoXSBtClv7IroRFllwtkKIJbDjmscKN5sG +mqg== X-Gm-Message-State: ALoCoQnHXWFPgKwvl1I7Z7J8+vdLB3fu3Z/je8ypoDHPonM5jaRK4oxjJ9z/7flDXrx5DjjyNbGq X-Received: by 10.194.120.68 with SMTP id la4mr5489781wjb.139.1431518554046; Wed, 13 May 2015 05:02:34 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-144-121-184.as13285.net. [78.144.121.184]) by mx.google.com with ESMTPSA id ei8sm32612912wjd.32.2015.05.13.05.02.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 05:02:33 -0700 (PDT) From: Srinivas Kandagatla To: Patrick Lai , Mark Brown Cc: Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Banajit Goswami , Kenneth Westfield , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v1 06/13] ASoC: qcom: make osr clock optional Date: Wed, 13 May 2015 13:02:27 +0100 Message-Id: <1431518547-7540-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431518302-7139-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1431518302-7139-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some LPASS integrations like on APQ8016 do not have OSR clk, so making osr clk optional would allow such integrations to use lpass driver. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass-cpu.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 0d28ea7..33e28370 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -33,6 +33,9 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; + if (IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + return 0; + ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); if (ret) dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n", @@ -47,18 +50,22 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->diver->id]); - if (ret) { - dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", - __func__, ret); - return ret; + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) { + ret = clk_prepare_enable( + drvdata->mi2s_osr_clk[dai->driver->id]); + if (ret) { + dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", + __func__, ret); + return ret; + } } ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n", __func__, ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); return ret; } @@ -71,7 +78,9 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, @@ -408,11 +417,13 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) else sprintf(clk_name, "mi2s-osr-clk"); - drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, clk_name); + drvdata->mi2s_osr_clk[i] = devm_clk_get(&pdev->dev, + clk_name); if (IS_ERR(drvdata->mi2s_osr_clk[i])) { - dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", - __func__, PTR_ERR(drvdata->mi2s_osr_clk[i])); - return PTR_ERR(drvdata->mi2s_osr_clk[i]); + dev_err(&pdev->dev, + "%s() error getting mi2s-osr-clk: %ld\n", + __func__, + PTR_ERR(drvdata->mi2s_osr_clk[i])); } }