From patchwork Sat May 16 12:32:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 6421631 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4D3F4C0432 for ; Sat, 16 May 2015 12:35:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6272A205B9 for ; Sat, 16 May 2015 12:35:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62E3520204 for ; Sat, 16 May 2015 12:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755066AbbEPMc6 (ORCPT ); Sat, 16 May 2015 08:32:58 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:34952 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755095AbbEPMcx (ORCPT ); Sat, 16 May 2015 08:32:53 -0400 Received: by wicmx19 with SMTP id mx19so22898397wic.0 for ; Sat, 16 May 2015 05:32:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0Tu9CYT4dtRSlShVcSLFPbb+ePiQ50W1hIErzD1yJq4=; b=Ze5H1RQHNFdYt2denOFq3T5Tb5uU+fzwlW8j2IEx3HYDCjKJ2yXb7iusR7r7/1/ZTu 1J3hgbWqWLeOPfKpXURwbi3y++qygI5RMK0nZYJgTe12ynUQL54pscLDsAlSuiz1Xwaw AEEUpC3NbXHZsZ71owoRXGXDa71FM6FjtXggQrQF6ckwTtmNYUjr6JIQLvm6E1OjiSzF 6UH0sdDnQ+oER9omgIypaFqMA4yUY0CdBw8DwnfExKZjciUVzFfabdWZ54lr4ERvJ93Y qvt9OzknA0dEeMq5ojLnAg/l9ijuF0V3XTPhduq5BVtPNAjJl+plNOtudv3Or1JKKaWL /fjw== X-Gm-Message-State: ALoCoQk33MZfgfLyV5EB3mjhtLz/VD1mPHox52FYmY9FqPMARSPMd59dVnNsP1x7hPW1KBLB6y4u X-Received: by 10.180.206.229 with SMTP id lr5mr5849257wic.86.1431779572747; Sat, 16 May 2015 05:32:52 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-144-121-184.as13285.net. [78.144.121.184]) by mx.google.com with ESMTPSA id j1sm2698607wia.22.2015.05.16.05.32.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 16 May 2015 05:32:52 -0700 (PDT) From: Srinivas Kandagatla To: Patrick Lai , Mark Brown Cc: Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Banajit Goswami , Kenneth Westfield , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 06/13] ASoC: qcom: make osr clock optional Date: Sat, 16 May 2015 13:32:49 +0100 Message-Id: <1431779569-2091-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431779462-1732-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1431779462-1732-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some LPASS integrations like on APQ8016 do not have OSR clk, so making osr clk optional would allow such integrations to use lpass driver. Tested-by: Kenneth Westfield Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass-cpu.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 86c9d1a..95369d8 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -33,6 +33,9 @@ static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; + if (IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + return 0; + ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); if (ret) dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n", @@ -47,18 +50,22 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); int ret; - ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->diver->id]); - if (ret) { - dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", - __func__, ret); - return ret; + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) { + ret = clk_prepare_enable( + drvdata->mi2s_osr_clk[dai->driver->id]); + if (ret) { + dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n", + __func__, ret); + return ret; + } } ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]); if (ret) { dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n", __func__, ret); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); return ret; } @@ -71,7 +78,9 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); - clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); + + if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) + clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); } static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, @@ -415,7 +424,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) dev_err(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", __func__, - return PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); + PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); } if (variant->num_dai > 1)