From patchwork Fri Jun 5 12:40:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 6553161 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3EC55C0020 for ; Fri, 5 Jun 2015 12:41:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 54AF0205B7 for ; Fri, 5 Jun 2015 12:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3E171206FA for ; Fri, 5 Jun 2015 12:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932670AbbFEMlb (ORCPT ); Fri, 5 Jun 2015 08:41:31 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:34367 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754578AbbFEMkt (ORCPT ); Fri, 5 Jun 2015 08:40:49 -0400 Received: by wibut5 with SMTP id ut5so19886628wib.1 for ; Fri, 05 Jun 2015 05:40:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NEaWlkLMiTngHeV6pUSn6/79leHyqNzNAlNB5SgNj60=; b=AlGp4UW1+FafvHlIPCq5yXdpjMTi0BHZL/RzE4sb4hIzO+ITySVyjCgC4rRhnJ7TQz tYLowb6L4DmOA3VkVHkB4ihBoZ0IzHDeCnZE0vqNurzYODB4c207ZjJq8svr1CIW9aP5 kYhG41sNhwMB0n7X2BhbocUd3XvPSuyW6sOAF9Qa+NcZZRAVKaR1NWKkEOj0+kfQHufp oiJ19cIj/hcZD7dK8QqzaRrK3egqCu4SM9PQHWluZDmuYIdBVgdli68rdXuENH5qjqAL fQqjkXx3ETK1+KkgadM0VY25eYz0IW/gDGu62n61rYDHp1Jylef+KbMkX0vB5fgt2lwP oWEA== X-Gm-Message-State: ALoCoQlDUH1h9VV6G15qOrRjkwF0uEDQtEl9jQbSWkOOA/s4wtf+feDHRXxg+EEXp6rzdinhcON4 X-Received: by 10.194.84.100 with SMTP id x4mr6302386wjy.69.1433508048726; Fri, 05 Jun 2015 05:40:48 -0700 (PDT) Received: from mms.wifi.mm-sol.com ([37.157.136.206]) by mx.google.com with ESMTPSA id l6sm3250172wib.18.2015.06.05.05.40.47 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jun 2015 05:40:48 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v2 4/5] clk: qcom: Add MSM8916 gpu clocks Date: Fri, 5 Jun 2015 15:40:35 +0300 Message-Id: <1433508036-28644-5-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1433508036-28644-1-git-send-email-georgi.djakov@linaro.org> References: <1433508036-28644-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the msm8916 bimc clocks that are needed for GPU. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/gcc-msm8916.c | 59 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8916.h | 3 ++ 2 files changed, 62 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index d493e9f3a2eb..9b4a8ebb1eb2 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -1094,6 +1094,28 @@ static struct clk_rcg2 apss_tcu_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { + F(100000000, P_GPLL0, 8, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266500000, P_BIMC, 4, 0, 0), + F(533000000, P_BIMC, 2, 0, 0), + { } +}; + +static struct clk_rcg2 bimc_gpu_clk_src = { + .cmd_rcgr = 0x31028, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .freq_tbl = ftbl_gcc_bimc_gpu_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_gpu_clk_src", + .parent_names = gcc_xo_gpll0_bimc, + .num_parents = 3, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { F(80000000, P_GPLL0, 10, 0, 0), { } @@ -2420,6 +2442,40 @@ static struct clk_branch gcc_gtcu_ahb_clk = { }, }; +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x31024, + .clkr = { + .enable_reg = 0x31024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk = { + .halt_reg = 0x31040, + .clkr = { + .enable_reg = 0x31040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_jpeg_tbu_clk = { .halt_reg = 0x12034, .clkr = { @@ -2749,6 +2805,9 @@ static struct clk_regmap *gcc_msm8916_clocks[] = { [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, + [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, }; static const struct qcom_reset_map gcc_msm8916_resets[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h index 53b39293d759..d54a9715c37e 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -155,5 +155,8 @@ #define BIMC_DDR_CLK_SRC 138 #define GCC_APSS_TCU_CLK 139 #define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 #endif