From patchwork Thu Aug 6 10:37:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6957911 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 10D87C05AC for ; Thu, 6 Aug 2015 10:40:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD60920688 for ; Thu, 6 Aug 2015 10:40:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E831D20680 for ; Thu, 6 Aug 2015 10:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932277AbbHFKkZ (ORCPT ); Thu, 6 Aug 2015 06:40:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39020 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932256AbbHFKkV (ORCPT ); Thu, 6 Aug 2015 06:40:21 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id ACFF21415AB; Thu, 6 Aug 2015 10:40:20 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 7E1761415C1; Thu, 6 Aug 2015 10:40:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DC0D214159E; Thu, 6 Aug 2015 10:40:08 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak Subject: [PATCH v8 13/13] clk: qcom: gdsc: Manage clocks with !CONFIG_PM Date: Thu, 6 Aug 2015 16:07:54 +0530 Message-Id: <1438857474-20262-14-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> References: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With CONFIG_PM disabled, turn the devices clocks on during driver binding to the device, and turn them off when the driver is unbound from the device. Platforms can specify all the clocks that need to be managed in !CONFIG_PM case using qcom_pm_add_notifier(). The use of pm_clk_add_notifier() isn't appropriate here since we need to only manage clocks with valid power domain associations done via DT, instead of what pm_clk_add_notifier() does, which is manage clocks for all on SoC/off SoC devices associating all of them to a dummy power domain instead Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 8 ++++++ 2 files changed, 82 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 20965fc..afc0b15 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -303,3 +304,76 @@ void gdsc_unregister(struct device *dev) { of_genpd_del_provider(dev->of_node); } + +#ifndef CONFIG_PM +static void enable_clock(struct of_phandle_args *clkspec) +{ + struct clk *clk; + + clk = of_clk_get_from_provider(clkspec); + if (!IS_ERR(clk)) { + clk_prepare_enable(clk); + clk_put(clk); + } +} + +static void disable_clock(struct of_phandle_args *clkspec) +{ + struct clk *clk; + + clk = of_clk_get_from_provider(clkspec); + if (!IS_ERR(clk)) { + clk_disable_unprepare(clk); + clk_put(clk); + } +} + +static int clk_notify(struct notifier_block *nb, unsigned long action, + void *data) +{ + int sz, i = 0; + struct device *dev = data; + struct gdsc_notifier_block *gdsc_nb; + struct of_phandle_args clkspec; + struct device_node *np = dev->of_node; + + if (!of_find_property(dev->of_node, "power-domains", &sz)) + return 0; + + gdsc_nb = container_of(nb, struct gdsc_notifier_block, nb); + + if (!gdsc_nb->clock_count) + return 0; + + switch (action) { + case BUS_NOTIFY_BIND_DRIVER: + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", + i, &clkspec)) { + if (match(clkspec.args[0], gdsc_nb->clocks, + gdsc_nb->clock_count)) + enable_clock(&clkspec); + i++; + } + break; + case BUS_NOTIFY_UNBOUND_DRIVER: + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", + i, &clkspec)) { + if (match(clkspec.args[0], gdsc_nb->clocks, + gdsc_nb->clock_count)) + disable_clock(&clkspec); + i++; + } + break; + } + return 0; +} + +void qcom_pm_add_notifier(struct gdsc_notifier_block *gdsc_nb) +{ + if (!gdsc_nb) + return; + + gdsc_nb->nb.notifier_call = clk_notify, + bus_register_notifier(&platform_bus_type, &gdsc_nb->nb); +} +#endif diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 0b958a6..b0a36ed 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -76,4 +76,12 @@ static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n, static inline void gdsc_unregister(struct device *d) {}; #endif /* CONFIG_QCOM_GDSC */ +#ifndef CONFIG_PM +struct gdsc_notifier_block { + struct notifier_block nb; + unsigned int *clocks; + unsigned int clock_count; +}; +void qcom_pm_add_notifier(struct gdsc_notifier_block *); +#endif /* !CONFIG_PM */ #endif /* __QCOM_GDSC_H__ */