From patchwork Thu Aug 13 14:48:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 7008721 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3D98F9F44C for ; Thu, 13 Aug 2015 14:49:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 43E68206CC for ; Thu, 13 Aug 2015 14:49:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25AD1207A6 for ; Thu, 13 Aug 2015 14:49:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753251AbbHMOsz (ORCPT ); Thu, 13 Aug 2015 10:48:55 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:35148 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752620AbbHMOsx (ORCPT ); Thu, 13 Aug 2015 10:48:53 -0400 Received: by wicne3 with SMTP id ne3so143074990wic.0 for ; Thu, 13 Aug 2015 07:48:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bT5ZV8bGqHPxkmStZkZA7f1OYlO86nhFuhwtT6DkAT4=; b=RSOTZx/ro8GWTeSVCOiUc/CrFP5Jb/DyPToU+iPpXRECTATP+gEu1piwmNNygljrGj wB9dtoOgy2Mxexpwe5Ktr/ik0kIrZ3+DHSk/cp4T2Se9ZPu0Kcf9s8TbBGNpKDU3cFj7 zJwynABt7H+JjmxmE39EsNK0/MDdNNgjktRgDwtIaENfjW5HbeFxDDBE5fZLhEIPncik Yp/hEYO8VrBbrNXjDuSSat/djpQF6yFPdlMwkd5zPvlnaleux0O65gooxv+0fiAZK0L/ KqfbnCIGHzHyNfl/BTHC039u1LJ19rFQgQVtBDoNTBPH4/uCRr0dhk1iso7Eix2/Uc6i 0C5Q== X-Gm-Message-State: ALoCoQm62EaDazRC6y+6iHIw00GRsljni/rtS1Zt0hbrCo7S2tI447rNiTi2CmbPw4u/jZDjuTP1 X-Received: by 10.180.216.42 with SMTP id on10mr61046747wic.3.1439477332617; Thu, 13 Aug 2015 07:48:52 -0700 (PDT) Received: from mms.wifi.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id hn2sm3706749wjc.45.2015.08.13.07.48.51 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 13 Aug 2015 07:48:51 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v3 2/4] clk: qcom: Add support for RCGs with shared branches Date: Thu, 13 Aug 2015 17:48:35 +0300 Message-Id: <1439477317-1902-3-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1439477317-1902-1-git-send-email-georgi.djakov@linaro.org> References: <1439477317-1902-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some root clock generators may have child branches that are controlled by different CPUs. These RCGs require some special operations: - some enable bits have to be toggled when we set the rate; - if RCG is disabled we only cache the rate and set it later when enabled; - when the RCG is disabled, the mux is set to the safe source; Signed-off-by: Georgi Djakov --- drivers/clk/qcom/clk-rcg.h | 4 ++- drivers/clk/qcom/clk-rcg2.c | 77 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 56028bb31d87..0693b9e0b15e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -153,8 +153,8 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @hid_width: number of bits in half integer divider * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table + * @current_freq: last cached frequency when using branches with shared RCGs * @clkr: regmap clock handle - * @lock: register lock * */ struct clk_rcg2 { @@ -163,12 +163,14 @@ struct clk_rcg2 { u8 hid_width; const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; + unsigned long current_freq; struct clk_regmap clkr; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) extern const struct clk_ops clk_rcg2_ops; +extern const struct clk_ops clk_rcg2_shared_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; extern const struct clk_ops clk_pixel_ops; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 9aec1761fd29..681faf2dcdc5 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -300,6 +300,83 @@ const struct clk_ops clk_rcg2_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg2_ops); +static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const char *name = clk_hw_get_name(hw); + int ret, count; + + /* force enable RCG */ + ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, CMD_ROOT_EN); + if (ret) + return ret; + + /* wait for RCG to turn ON */ + for (count = 500; count > 0; count--) { + ret = clk_rcg2_is_enabled(hw); + if (ret) + break; + udelay(1); + } + if (!count) + pr_err("%s: RCG did not turn on\n", name); + + /* set clock rate */ + ret = __clk_rcg2_set_rate(hw, rate); + if (ret) + return ret; + + /* clear force enable RCG */ + return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); +} + +static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* cache the rate */ + rcg->current_freq = rate; + + if (!__clk_is_enabled(hw->clk)) + return 0; + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static int clk_rcg2_shared_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const char *name = clk_hw_get_name(hw); + + if (!rcg->current_freq) { + pr_err("%s: Please set rate before enabling\n", name); + rcg->current_freq = rcg->freq_tbl[0].freq; + } + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static void clk_rcg2_shared_disable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* switch to XO, which is the lowest entry in the freq table */ + clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0); +} + +const struct clk_ops clk_rcg2_shared_ops = { + .enable = clk_rcg2_shared_enable, + .disable = clk_rcg2_shared_disable, + .get_parent = clk_rcg2_get_parent, + .recalc_rate = clk_rcg2_recalc_rate, + .determine_rate = clk_rcg2_determine_rate, + .set_rate = clk_rcg2_shared_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); + struct frac_entry { int num; int den;