From patchwork Thu Aug 27 17:37:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 7086511 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B4B39F358 for ; Thu, 27 Aug 2015 17:39:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 96EEA209DB for ; Thu, 27 Aug 2015 17:39:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B3CB4209BC for ; Thu, 27 Aug 2015 17:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754011AbbH0RjL (ORCPT ); Thu, 27 Aug 2015 13:39:11 -0400 Received: from seldrel01.sonyericsson.com ([37.139.156.2]:15100 "EHLO seldrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751667AbbH0RiG (ORCPT ); Thu, 27 Aug 2015 13:38:06 -0400 From: Bjorn Andersson To: Alexandre Courbot , Ian Campbell , Linus Walleij , Mark Rutland , Pawel Moll , Rob Herring CC: , , , Subject: [PATCH 1/4] dt-binding: gpio: Add Qualcomm SMSM device tree documentation Date: Thu, 27 Aug 2015 10:37:55 -0700 Message-ID: <1440697078-4106-2-git-send-email-bjorn.andersson@sonymobile.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: <1440697078-4106-1-git-send-email-bjorn.andersson@sonymobile.com> References: <1440697078-4106-1-git-send-email-bjorn.andersson@sonymobile.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This documents a device tree binding for exposing the Qualcomm Shared Memory State Machine as a set of gpio- and interrupt-controllers. Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/gpio/qcom,smsm.txt | 114 +++++++++++++++++++++ drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + 3 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/qcom,smsm.txt diff --git a/Documentation/devicetree/bindings/gpio/qcom,smsm.txt b/Documentation/devicetree/bindings/gpio/qcom,smsm.txt new file mode 100644 index 000000000000..06201ba76594 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/qcom,smsm.txt @@ -0,0 +1,114 @@ +Qualcomm Shared Memory State Machine + +The Shared Memory State Machine facilitates broadcasting of single bit state +information between the processors in a Qualcomm SoC. Each processor is +assigned 32 bits of state that can be modified. A processor can through a +matrix of bitmaps signal subscription of notifications upon changes to a +certain bit owned by a certain remote processor. + +This document defines the binding for a driver that implements and exposes this +a GPIO controller and a set of interrupt controllers. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,smsm" + +- qcom,ipc-N: + Usage: required + Value type: + Definition: three entries specifying the outgoing ipc bit used for + signaling the N:th remote processor + - phandle to a syscon node representing the apcs registers + - u32 representing offset to the register within the syscon + - u32 representing the ipc bit within the register + +- qcom,local-host: + Usage: optional + Value type: + Definition: identifier of the local processor in the list of hosts, or + in other words specifier of the column in the subscription + matrix representing the local processor + defaults to host 0 + +- #address-cells: + Usage: required + Value type: + Definition: must be 1 + +- #size-cells: + Usage: required + Value type: + Definition: must be 0 + += SUBNODES +Each processor's state bits are described by a subnode of the smsm device node. +A node can either be a gpio-controller - denoting the local processors bits - +or an interrupt-controller - denoting a remote processors state bits. The node +names are not important. + +- reg: + Usage: required + Value type: + Definition: specifies the offset, in words, of the first bit for this + entry + +- gpio-controller: + Usage: required for local entry + Value type: + Definition: marks the entry as a gpio-controller and the state bits to + belong to the local processor + +- #gpio-cells: + Usage: required for local entry + Value type: + Definition: must be 2 - denotes bit number and GPIO flags + +- interrupt-controller: + Usage: required for remote entries + Value type: + Definition: marks the entry as a interrupt-controller and the state bits + to belong to a remote processor + +- #interrupt-cells: + Usage: required for remote entries + Value type: + Definition: must be 2 - denotes bit number and IRQ flags + +- interrupts: + Usage: required for remote entries + Value type: + Definition: one entry specifying remote IRQ used by the remote processor + to signal changes of its state bits + + += EXAMPLE +The following example shows the SMEM setup for controlling properties of the +wireless processor, defined from the 8974 apps processor's point-of-view. It +encompasses one outbound entry and the outgoing interrupt for the wireless +processor. + +smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = <0 144 1>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b4fc9e4d24c6..0e57b60faae8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -354,6 +354,14 @@ config GPIO_PXA help Say yes here to support the PXA GPIO device +config GPIO_QCOM_SMSM + bool "Qualcomm Shared Memory State Machine" + depends on QCOM_SMEM + help + Say yes here to support the Qualcomm Shared Memory State Machine. + The state machine is represented by bits in shared memory and is + exposed to the system as GPIOs. + config GPIO_RCAR tristate "Renesas R-Car GPIO" depends on ARM && (ARCH_SHMOBILE || COMPILE_TEST) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index f79a7c482a99..0fd213892403 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o +obj-$(CONFIG_GPIO_QCOM_SMSM) += gpio-qcom-smsm.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o