From patchwork Wed Sep 16 13:24:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 7194751 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5BD3F9F380 for ; Wed, 16 Sep 2015 13:25:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6770620861 for ; Wed, 16 Sep 2015 13:25:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 677EB20838 for ; Wed, 16 Sep 2015 13:25:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753450AbbIPNZA (ORCPT ); Wed, 16 Sep 2015 09:25:00 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:37374 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753425AbbIPNY6 (ORCPT ); Wed, 16 Sep 2015 09:24:58 -0400 Received: by wicfx3 with SMTP id fx3so70439853wic.0 for ; Wed, 16 Sep 2015 06:24:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PFleLV+RSb1ewLg+RA+NJTw/okKqv7r0zVta42DqLcc=; b=mw2qLMvcwZbDWniW7D/1Tco+Rcu518uu+dyA/WDpF35d6pfBdlz6g2ZCYhNMC30kZX B+dCJ82ps5nasvsuHX/tel/Zom7LoBIavyHd4s2LQZbmOX8JtIEQANUrWlSoBNt8ltx8 Lj/IFkYCcd7LekuhK+dBY616p59i3ot5AzhC9DqzFcJ0dHUPPG30qZ0NxX/vbKgPXeKq GBgDhZr4GdQpyhv96Yiguy8gpeHPTcZ2xunwg/Mvtb15Ms7uuzf1KmRG1asyNW2mD3Vc Q0gmaM9N+E3YGEa2gawgj281t5G19NcShrLRKcD2EvXlcgTvyUwk4F8gnUYwa1O+ZaVq /k+Q== X-Gm-Message-State: ALoCoQkVw8Df2zxDees/Y+5s9eIdi1a7M2JOrJfgqw8OsT+5Z+T82j5dxwFUQCfSMQs2AOLks1cW X-Received: by 10.194.116.67 with SMTP id ju3mr50390759wjb.143.1442409897132; Wed, 16 Sep 2015 06:24:57 -0700 (PDT) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id ej5sm26610019wjd.22.2015.09.16.06.24.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2015 06:24:56 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v4 3/4] clk: qcom: Add MSM8916 gpu clocks Date: Wed, 16 Sep 2015 16:24:47 +0300 Message-Id: <1442409888-19917-4-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442409888-19917-1-git-send-email-georgi.djakov@linaro.org> References: <1442409888-19917-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the msm8916 BIMC (Bus Integrated Memory Controller) clocks that are needed for GPU. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/gcc-msm8916.c | 61 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8916.h | 3 ++ 2 files changed, 64 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index ad9316751eb2..bd87a3e2cbeb 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -1083,6 +1083,30 @@ static struct clk_rcg2 apss_tcu_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266500000, P_BIMC, 4, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(533000000, P_BIMC, 2, 0, 0), + { } +}; + +static struct clk_rcg2 bimc_gpu_clk_src = { + .cmd_rcgr = 0x31028, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .freq_tbl = ftbl_gcc_bimc_gpu_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_gpu_clk_src", + .parent_names = gcc_xo_gpll0_bimc, + .num_parents = 3, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { F(80000000, P_GPLL0, 10, 0, 0), { } @@ -2409,6 +2433,40 @@ static struct clk_branch gcc_gtcu_ahb_clk = { }, }; +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x31024, + .clkr = { + .enable_reg = 0x31024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk = { + .halt_reg = 0x31040, + .clkr = { + .enable_reg = 0x31040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_jpeg_tbu_clk = { .halt_reg = 0x12034, .clkr = { @@ -2778,6 +2836,9 @@ static struct clk_regmap *gcc_msm8916_clocks[] = { [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, + [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, }; static struct gdsc *gcc_msm8916_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h index 9169ae656c77..d21501bb3d52 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -155,6 +155,9 @@ #define BIMC_DDR_CLK_SRC 138 #define GCC_APSS_TCU_CLK 139 #define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 /* Indexes for GDSCs */ #define BIMC_GDSC 0