From patchwork Thu Sep 17 16:39:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 7209111 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1546D9F39B for ; Thu, 17 Sep 2015 16:42:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 578F4207C0 for ; Thu, 17 Sep 2015 16:42:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FAD8207B8 for ; Thu, 17 Sep 2015 16:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753024AbbIQQlX (ORCPT ); Thu, 17 Sep 2015 12:41:23 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:34457 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752275AbbIQQkW (ORCPT ); Thu, 17 Sep 2015 12:40:22 -0400 Received: by wicfx3 with SMTP id fx3so31770987wic.1 for ; Thu, 17 Sep 2015 09:40:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8dvSCD0iIKKJKs4I/QqJnfnQHouDCTL9mL2iic8m8LY=; b=Q+zMCapi2+Hwck3Gds0IFCxS9urlQuS0AMzJc3HBrnF2f+9kRFzvnvnZDnKalpA/BW eBW+qp5Cbm+fyFpfzEfK7ZdN02IbbROqjXsuo16v/6Z/Qipq55oITvZu0qVmVJ+vYs/+ R4JxvKVsJ2dap4rhlF0uALfhpRLIAgfdxzhLPignXcjOsyPXBzm1AnFSY8hZK6BiRjng QKBDL0IdyNWezwUFn9Z/6mN0s3pMfh5h9vgXtZR0g35ybgkhlAW/g0qnbyJlfxKWSKkb zM3/G4fNcLySu1nrnLwfFohAoxliDmb5tULlC6U4UQUTjn/cWf6tgT0Te9IH8xX2Nqe5 EDBg== X-Gm-Message-State: ALoCoQnaqRlv4xlpmEgceXbKx+8I/o/b2GMkAauGYLZyyQDLfAiBMbIR5VjPcdfxqwIYoSGX4G+I X-Received: by 10.180.84.102 with SMTP id x6mr32407857wiy.75.1442508020478; Thu, 17 Sep 2015 09:40:20 -0700 (PDT) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id f17sm4260519wjn.38.2015.09.17.09.40.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Sep 2015 09:40:19 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 2/4] clk: qcom: Add support for RCGs with shared branches Date: Thu, 17 Sep 2015 19:39:27 +0300 Message-Id: <1442507969-18062-3-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442507969-18062-1-git-send-email-georgi.djakov@linaro.org> References: <1442507969-18062-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some root clock generators may have child branches that are controlled by different CPUs. These RCGs require some special operations: - some enable bits have to be toggled when we set the rate; - if RCG is disabled we only cache the rate and set it later when enabled; - when the RCG is disabled, the mux is set to the safe source; Signed-off-by: Georgi Djakov --- drivers/clk/qcom/clk-rcg.h | 4 +- drivers/clk/qcom/clk-rcg2.c | 91 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 31f92d70e8e0..5012e5b90cfb 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -153,8 +153,8 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @hid_width: number of bits in half integer divider * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table + * @current_freq: last cached frequency when using branches with shared RCGs * @clkr: regmap clock handle - * @lock: register lock * */ struct clk_rcg2 { @@ -163,12 +163,14 @@ struct clk_rcg2 { u8 hid_width; const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; + unsigned long current_freq; struct clk_regmap clkr; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) extern const struct clk_ops clk_rcg2_ops; +extern const struct clk_ops clk_rcg2_shared_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; extern const struct clk_ops clk_byte2_ops; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index d941dea6f7c7..c7b9b32742e5 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -300,6 +300,97 @@ const struct clk_ops clk_rcg2_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg2_ops); +static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const char *name = clk_hw_get_name(hw); + int ret, count; + + /* force enable RCG */ + ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, CMD_ROOT_EN); + if (ret) + return ret; + + /* wait for RCG to turn ON */ + for (count = 500; count > 0; count--) { + ret = clk_rcg2_is_enabled(hw); + if (ret) + break; + udelay(1); + } + if (!count) + pr_err("%s: RCG did not turn on\n", name); + + /* set clock rate */ + ret = __clk_rcg2_set_rate(hw, rate); + if (ret) + return ret; + + /* clear force enable RCG */ + return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); +} + +static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* cache the rate */ + rcg->current_freq = rate; + + if (!__clk_is_enabled(hw->clk)) + return 0; + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static unsigned long +clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + unsigned long rate; + u32 cfg, hid_div, mask; + + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + + mask = BIT(rcg->hid_width) - 1; + hid_div = cfg >> CFG_SRC_DIV_SHIFT; + hid_div &= mask; + + rate = (parent_rate * 2) / (hid_div + 1); + + rcg->current_freq = rate; + + return rate; +} + +static int clk_rcg2_shared_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static void clk_rcg2_shared_disable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* switch to XO, which is the lowest entry in the freq table */ + clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0); +} + +const struct clk_ops clk_rcg2_shared_ops = { + .enable = clk_rcg2_shared_enable, + .disable = clk_rcg2_shared_disable, + .get_parent = clk_rcg2_get_parent, + .recalc_rate = clk_rcg2_shared_recalc_rate, + .determine_rate = clk_rcg2_determine_rate, + .set_rate = clk_rcg2_shared_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); + struct frac_entry { int num; int den;