From patchwork Thu Sep 17 16:39:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 7209051 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 569E1BEEC1 for ; Thu, 17 Sep 2015 16:41:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DDF5203C2 for ; Thu, 17 Sep 2015 16:41:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 61D6420384 for ; Thu, 17 Sep 2015 16:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752864AbbIQQk7 (ORCPT ); Thu, 17 Sep 2015 12:40:59 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:36698 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752357AbbIQQkX (ORCPT ); Thu, 17 Sep 2015 12:40:23 -0400 Received: by wicgb1 with SMTP id gb1so125819163wic.1 for ; Thu, 17 Sep 2015 09:40:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PFleLV+RSb1ewLg+RA+NJTw/okKqv7r0zVta42DqLcc=; b=FFArj+zB2gi8HZ9x2qhd5rN6NAt3QEl0ag/+AoH+ekZ+Kf7xDs/n85t828A+dFx89d TyOT3KP6zXOlN2pWNzi6yNC8zNF2cyB1kU1WdFvSrsvGi2Zb/X0xmDpXgiIECmRq23lG 4bcXIDIzDJDIs7FG1mlF4Qj/C+wtL1VN6ZncFoH8blLE8AF4p3iYgn9wHf/YPcrBZt/V JkYQ1Sk4Dcf+37JnB7JGThMbFZARIsTvW2D3dmUtrIjM8UbMdN/xFt9C3kPd0QF9UC9h d0xiyabp4Ha5Ml42Jhb0K3VvIsHM2vOAcXcknKs3jf7vkKc8Z52zlwtmNFkrmVrWURQw JQVA== X-Gm-Message-State: ALoCoQncTdZtMrLi0CQQ27K2BvlFGSSP9FN0e6viOmOe18xD/nZfLXFVseHKbuNHqgl5ywbWV5Zb X-Received: by 10.180.86.138 with SMTP id p10mr9748309wiz.39.1442508022028; Thu, 17 Sep 2015 09:40:22 -0700 (PDT) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id f17sm4260519wjn.38.2015.09.17.09.40.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Sep 2015 09:40:20 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 3/4] clk: qcom: Add MSM8916 gpu clocks Date: Thu, 17 Sep 2015 19:39:28 +0300 Message-Id: <1442507969-18062-4-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442507969-18062-1-git-send-email-georgi.djakov@linaro.org> References: <1442507969-18062-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the msm8916 BIMC (Bus Integrated Memory Controller) clocks that are needed for GPU. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/gcc-msm8916.c | 61 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8916.h | 3 ++ 2 files changed, 64 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index ad9316751eb2..bd87a3e2cbeb 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -1083,6 +1083,30 @@ static struct clk_rcg2 apss_tcu_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266500000, P_BIMC, 4, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(533000000, P_BIMC, 2, 0, 0), + { } +}; + +static struct clk_rcg2 bimc_gpu_clk_src = { + .cmd_rcgr = 0x31028, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .freq_tbl = ftbl_gcc_bimc_gpu_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_gpu_clk_src", + .parent_names = gcc_xo_gpll0_bimc, + .num_parents = 3, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { F(80000000, P_GPLL0, 10, 0, 0), { } @@ -2409,6 +2433,40 @@ static struct clk_branch gcc_gtcu_ahb_clk = { }, }; +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x31024, + .clkr = { + .enable_reg = 0x31024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk = { + .halt_reg = 0x31040, + .clkr = { + .enable_reg = 0x31040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_jpeg_tbu_clk = { .halt_reg = 0x12034, .clkr = { @@ -2778,6 +2836,9 @@ static struct clk_regmap *gcc_msm8916_clocks[] = { [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, + [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, }; static struct gdsc *gcc_msm8916_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h index 9169ae656c77..d21501bb3d52 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -155,6 +155,9 @@ #define BIMC_DDR_CLK_SRC 138 #define GCC_APSS_TCU_CLK 139 #define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 /* Indexes for GDSCs */ #define BIMC_GDSC 0