From patchwork Tue Oct 6 23:48:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 7340701 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9BE07BEEA4 for ; Tue, 6 Oct 2015 23:49:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93EB92069B for ; Tue, 6 Oct 2015 23:48:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 632EA2066D for ; Tue, 6 Oct 2015 23:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752754AbbJFXs5 (ORCPT ); Tue, 6 Oct 2015 19:48:57 -0400 Received: from mail-qk0-f169.google.com ([209.85.220.169]:33356 "EHLO mail-qk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752313AbbJFXs5 (ORCPT ); Tue, 6 Oct 2015 19:48:57 -0400 Received: by qkas79 with SMTP id s79so556315qka.0 for ; Tue, 06 Oct 2015 16:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yuGt3XmanwxaqxWTYjb1N3hgwQ4VHkK5LIzYjHh+4gs=; b=iJtEHfFegDKF1dd3rW1nwjxK6yfMsrcc723YK8o0cMw5mi9jkivX4sWM04fcuEH4ER FZQkvmTeVs7Xy5Hy+0dZuNvzQhjTN7Vb65elDaVwuVZmuBp7JHiEHHndxOLrmc2DGwpd YpGGBUWT37i4D35cDw/RKXuhHsHU02+YxX82m9dKFESBAAK4U/CM2YqG5xp1sN+P6ISw 2kDUNaJoqjGMPmflxDHnThHh/OhWYpfOeigi4KTLOn39AFgn+Hn+d5L8RxyarQSx4JEZ tsZklYdMvpxU0G5xomsLoT4VEIQEcf3HseqsM6oHoZdN+ArXzPX3JFDzYRpIzXhuGELG a0gw== X-Received: by 10.55.51.84 with SMTP id z81mr50819836qkz.21.1444175336132; Tue, 06 Oct 2015 16:48:56 -0700 (PDT) Received: from localhost ([2601:184:4000:26d7:6af7:28ff:fe77:e429]) by smtp.gmail.com with ESMTPSA id c17sm177200qkj.31.2015.10.06.16.48.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 16:48:55 -0700 (PDT) From: Rob Clark To: linux-arm-msm@vger.kernel.org Cc: Bjorn Andersson , Andy Gross , Stephen Boyd , Rob Clark Subject: [PATCH] qcom-scm: add support to restore secure config Date: Tue, 6 Oct 2015 19:48:45 -0400 Message-Id: <1444175325-29227-1-git-send-email-robdclark@gmail.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Needed by OCMEM driver. Signed-off-by: Rob Clark --- Note: no objections to the device-id enum on mailing list and positive feedback on ##linux-msm so squashing that part in and re-sending drivers/firmware/qcom_scm-32.c | 20 ++++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 5 +++++ drivers/firmware/qcom_scm.c | 22 ++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 5 +++++ include/linux/qcom_scm.h | 13 +++++++++++++ 5 files changed, 65 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c1e4325..a7bf6d4 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -500,6 +500,26 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) req, req_cnt * sizeof(*req), resp, sizeof(*resp)); } +int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) +{ + int ret, scm_ret = 0; + struct msm_scm_sec_cfg { + __le32 id; + __le32 ctx_bank_num; + } cfg; + + cfg.id = cpu_to_le32(sec_id); + cfg.ctx_bank_num = cpu_to_le32(sec_id); + + ret = qcom_scm_call(QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG, + &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret)); + + if (ret || scm_ret) + return ret ? ret : -EINVAL; + + return 0; +} + bool __qcom_scm_pas_supported(u32 peripheral) { __le32 out; diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index e64fd92..7329cf0f 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -62,6 +62,11 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) return -ENOTSUPP; } +int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) +{ + return -ENOTSUPP; +} + bool __qcom_scm_pas_supported(u32 peripheral) { return false; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 39082c1..c9c99a3 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -154,6 +154,28 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) EXPORT_SYMBOL(qcom_scm_hdcp_req); /** + * qcom_scm_restore_sec_config_available() - Check if secure environment + * supports restore security config interface. + * + * Return true if restore-cfg interface is supported, false if not. + */ +bool qcom_scm_restore_sec_config_available(void) +{ + return __qcom_scm_is_call_available(QCOM_SCM_MP_SVC, + QCOM_SCM_MP_RESTORE_SEC_CFG); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config_available); + +/** + * qcom_scm_restore_sec_config() - call restore-cfg interface + */ +int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id) +{ + return __qcom_scm_restore_sec_config(sec_id, 0); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config); + +/** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial * @peripheral: peripheral id diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 220d19c..3085616 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -36,6 +36,11 @@ extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id); extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +#define QCOM_SCM_MP_SVC 0xc +#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x2 + +extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num); + #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index e407c0a..ee31eec 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -32,6 +32,19 @@ extern bool qcom_scm_hdcp_available(void); extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +enum qcom_scm_sec_dev_id { + QCOM_SCM_MDSS_DEV_ID = 1, + QCOM_SCM_OCMEM_DEV_ID = 5, + QCOM_SCM_PCIE0_DEV_ID = 11, + QCOM_SCM_PCIE1_DEV_ID = 12, + QCOM_SCM_GFX_DEV_ID = 18, + QCOM_SCM_UFS_DEV_ID = 19, + QCOM_SCM_ICE_DEV_ID = 20, +}; + +extern bool qcom_scm_restore_sec_config_available(void); +extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id); + extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);