From patchwork Tue Oct 6 23:49:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 7340711 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A501FBEEA4 for ; Tue, 6 Oct 2015 23:49:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9901D2069B for ; Tue, 6 Oct 2015 23:49:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7555520678 for ; Tue, 6 Oct 2015 23:49:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752713AbbJFXto (ORCPT ); Tue, 6 Oct 2015 19:49:44 -0400 Received: from mail-qg0-f45.google.com ([209.85.192.45]:36207 "EHLO mail-qg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751829AbbJFXto (ORCPT ); Tue, 6 Oct 2015 19:49:44 -0400 Received: by qgx61 with SMTP id 61so1046793qgx.3 for ; Tue, 06 Oct 2015 16:49:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZF1RgffvsVPrWlRtq3p+dS9F41A+auniwH/wYsnFs+8=; b=i/bHOaTYGxTZkjdX5sHgCskOi6gU6vpRzTjqG61F7FuU7yOUHvMwsxzY9/rwawEn5k NaT4qDypEHFS7m3xF2C8x4SOmsoRhtcQbwOC9rIKUo7637zNTK9hwIblw806Yafg6hM3 Kr6n0HdBvVfGahBaK0k+pG3KB5qhhOxc33FVNdYje0jdcsEcy0VT2wOCwJru9TQ9brnH 3RVp+i2a3gs7YnOw2ainD6kdjs0l8l6oy5+7w2IYVKIM+MiTHOlTxEWMfTnPH/CY43GR hYGFOrZ6e/tS8QYA85xLBJaBZhr+kRQUTWeuRlUXwJbG4JV7W0trrAAfNmqfgrCn+xHs VhYA== X-Received: by 10.140.144.23 with SMTP id 23mr53586886qhq.38.1444175383690; Tue, 06 Oct 2015 16:49:43 -0700 (PDT) Received: from localhost ([2601:184:4000:26d7:6af7:28ff:fe77:e429]) by smtp.gmail.com with ESMTPSA id 65sm14916631qha.41.2015.10.06.16.49.43 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 16:49:43 -0700 (PDT) From: Rob Clark To: linux-arm-msm@vger.kernel.org Cc: Bjorn Andersson , Andy Gross , Stephen Boyd , Rob Clark Subject: [PATCH] qcom-scm: add OCMEM lock/unlock interface Date: Tue, 6 Oct 2015 19:49:40 -0400 Message-Id: <1444175380-29322-1-git-send-email-robdclark@gmail.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Needed to enable device access to OCMEM. Signed-off-by: Rob Clark --- Note: no objections to the client-id enum on mailing list and positive feedback on ##linux-msm so squashing that part in and re-sending drivers/firmware/qcom_scm-32.c | 34 ++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 11 +++++++++++ drivers/firmware/qcom_scm.c | 39 +++++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 7 +++++++ include/linux/qcom_scm.h | 14 ++++++++++++++ 5 files changed, 105 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index a7bf6d4..dc84771b 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -520,6 +520,40 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) return 0; } +int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode) +{ + struct ocmem_tz_lock { + __le32 id; + __le32 offset; + __le32 size; + __le32 mode; + } request; + + request.id = cpu_to_le32(id); + request.offset = cpu_to_le32(offset); + request.size = cpu_to_le32(size); + request.mode = cpu_to_le32(mode); + + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD, + &request, sizeof(request), NULL, 0); +} + +int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size) +{ + struct ocmem_tz_unlock { + __le32 id; + __le32 offset; + __le32 size; + } request; + + request.id = cpu_to_le32(id); + request.offset = cpu_to_le32(offset); + request.size = cpu_to_le32(size); + + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD, + &request, sizeof(request), NULL, 0); +} + bool __qcom_scm_pas_supported(u32 peripheral) { __le32 out; diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 7329cf0f..0ca20a3 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -67,6 +67,17 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) return -ENOTSUPP; } +int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size, + uint32_t mode) +{ + return -ENOTSUPP; +} + +int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size) +{ + return -ENOTSUPP; +} + bool __qcom_scm_pas_supported(u32 peripheral) { return false; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index c9c99a3..5c5841d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -176,6 +176,45 @@ int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id) EXPORT_SYMBOL(qcom_scm_restore_sec_config); /** + * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available + */ +bool qcom_scm_ocmem_lock_available(void) +{ + return __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC, + QCOM_SCM_OCMEM_LOCK_CMD); +} +EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); + +/** + * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM + * region to the specified initiator + * + * @id: tz initiator id + * @offset: OCMEM offset + * @size: OCMEM size + * @mode: access mode (WIDE/NARROW) + */ +int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, u32 mode) +{ + return __qcom_scm_ocmem_lock(id, offset, size, mode); +} +EXPORT_SYMBOL(qcom_scm_ocmem_lock); + +/** + * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM + * region from the specified initiator + * + * @id: tz initiator id + * @offset: OCMEM offset + * @size: OCMEM size + */ +int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) +{ + return __qcom_scm_ocmem_unlock(id, offset, size); +} +EXPORT_SYMBOL(qcom_scm_ocmem_unlock); + +/** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial * @peripheral: peripheral id diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 3085616..ec3435e 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -41,6 +41,13 @@ extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num); +#define QCOM_SCM_OCMEM_SVC 0xf +#define QCOM_SCM_OCMEM_LOCK_CMD 0x1 +#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2 + +extern int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode); +extern int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size); + #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index ee31eec..41ad996 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -45,6 +45,20 @@ enum qcom_scm_sec_dev_id { extern bool qcom_scm_restore_sec_config_available(void); extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id); +enum qcom_scm_ocmem_client { + QCOM_SCM_OCMEM_UNUSED_ID = 0x0, + QCOM_SCM_OCMEM_GRAPHICS_ID, + QCOM_SCM_OCMEM_VIDEO_ID, + QCOM_SCM_OCMEM_LP_AUDIO_ID, + QCOM_SCM_OCMEM_SENSORS_ID, + QCOM_SCM_OCMEM_OTHER_OS_ID, + QCOM_SCM_OCMEM_DEBUG_ID, +}; + +extern bool qcom_scm_ocmem_lock_available(void); +extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, u32 mode); +extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size); + extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);