From patchwork Fri Nov 20 08:35:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 7665821 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 89F279F2E2 for ; Fri, 20 Nov 2015 08:38:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B59AE20498 for ; Fri, 20 Nov 2015 08:38:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF9BD20499 for ; Fri, 20 Nov 2015 08:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1162180AbbKTIhW (ORCPT ); Fri, 20 Nov 2015 03:37:22 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39963 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161228AbbKTIfi (ORCPT ); Fri, 20 Nov 2015 03:35:38 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 31A561401A7; Fri, 20 Nov 2015 08:35:38 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 20FAD1401AC; Fri, 20 Nov 2015 08:35:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A60551401A7; Fri, 20 Nov 2015 08:35:37 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: Felipe Balbi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Greg KH , devicetree@vger.kernel.org, Kishon Vijay Abraham I , Andy Gross Subject: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register Date: Fri, 20 Nov 2015 02:35:07 -0600 Message-Id: <1448008509-8913-3-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> References: <1448008509-8913-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds automatic configuration of the TCSR phy mux register based on the syscon-tcsr devicetree entry. This configuration is optional, as some platforms may not require the mux selection. Signed-off-by: Andy Gross --- drivers/usb/dwc3/dwc3-qcom.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 0880260..fcf264c 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include struct dwc3_qcom { struct device *dev; @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; struct dwc3_qcom *qdwc; + struct regmap *regmap; + u32 mux_offset; + u32 mux_bit; int ret; qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL); @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev) qdwc->sleep_clk = NULL; } + /* look for tcsr and if present, provision it */ + regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); + if (!IS_ERR(regmap)) { + if (of_property_read_u32_index(node, "syscon-tcsr", 1, + &mux_offset)) { + dev_err(qdwc->dev, "missing USB TCSR mux offset\n"); + return -EINVAL; + } + if (of_property_read_u32_index(node, "syscon-tcsr", 2, + &mux_bit)) { + dev_err(qdwc->dev, "missing USB TCSR mux bit\n"); + return -EINVAL; + } + + regmap_update_bits(regmap, mux_offset, BIT(mux_bit), + BIT(mux_bit)); + } else { + dev_info(qdwc->dev, "missing syscon tcsr entry\n"); + } + ret = clk_prepare_enable(qdwc->core_clk); if (ret) { dev_err(qdwc->dev, "failed to enable core clock\n");