From patchwork Fri Nov 20 08:35:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 7665771 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EC33E9F2E2 for ; Fri, 20 Nov 2015 08:36:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 20E8120497 for ; Fri, 20 Nov 2015 08:36:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 339D520437 for ; Fri, 20 Nov 2015 08:36:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1162045AbbKTIgh (ORCPT ); Fri, 20 Nov 2015 03:36:37 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39971 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1162192AbbKTIfj (ORCPT ); Fri, 20 Nov 2015 03:35:39 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 5936F1401AE; Fri, 20 Nov 2015 08:35:39 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 4A30F1401B0; Fri, 20 Nov 2015 08:35:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B78FB1401AE; Fri, 20 Nov 2015 08:35:38 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: Felipe Balbi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Greg KH , devicetree@vger.kernel.org, Kishon Vijay Abraham I , Andy Gross Subject: [PATCH 3/4] ARM: dts: qcom: Add DWC3 USB support on IPQ8064 Date: Fri, 20 Nov 2015 02:35:08 -0600 Message-Id: <1448008509-8913-4-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> References: <1448008509-8913-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Qualcomm DWC3 USB nodes to device tree to enable support for the DWC3 controller found on IPQ8064/AP148 platforms. Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 24 +++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 89 ++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index d501382..bf1638c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -97,5 +97,29 @@ sata@29000000 { status = "ok"; }; + + phy@100f8800 { + status = "ok"; + }; + + phy@100f8830 { + status = "ok"; + }; + + usb30@0 { + status = "ok"; + }; + + phy@110f8800 { + status = "ok"; + }; + + phy@110f8830 { + status = "ok"; + }; + + usb30@1 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index fa69863..b2dcd9d 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -329,5 +329,94 @@ #reset-cells = <1>; }; + hs_phy_0: phy@100f8800 { + compatible = "qcom,dwc3-hs-usb-phy"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + ss_phy_0: phy@100f8830 { + compatible = "qcom,dwc3-ss-usb-phy"; + reg = <0x100f8830 0x30>; + + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + usb30@0 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + syscon-tcsr = <&tcsr 0xb0 1>; + + ranges; + + status = "disabled"; + + dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <0 205 0x4>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,dwc3-hs-usb-phy"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,dwc3-ss-usb-phy"; + reg = <0x110f8830 0x30>; + + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + usb30@1 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + syscon-tcsr = <&tcsr 0xb0 0>; + + ranges; + + status = "disabled"; + + dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <0 110 0x4>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + }; + }; }; };