diff mbox

[4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage

Message ID 1448008509-8913-5-git-send-email-agross@codeaurora.org (mailing list archive)
State Not Applicable, archived
Delegated to: Andy Gross
Headers show

Commit Message

Andy Gross Nov. 20, 2015, 8:35 a.m. UTC
This patch adds documentation for the optional syscon-tcsr property in the
Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
configure the TCSR USB phy mux register.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Rob Herring (Arm) Nov. 20, 2015, 2:33 p.m. UTC | #1
On Fri, Nov 20, 2015 at 02:35:09AM -0600, Andy Gross wrote:
> This patch adds documentation for the optional syscon-tcsr property in the
> Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
> configure the TCSR USB phy mux register.
> 
> Signed-off-by: Andy Gross <agross@codeaurora.org>

Acked-by: Rob Herring <robh@kernel.org>

> ---
>  Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> index ca164e7..dfa222d 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> @@ -8,6 +8,10 @@ Required properties:
>    "core"		Master/Core clock, have to be >= 125 MHz for SS
>  				operation and >= 60MHz for HS operation
>  
> +Optional properties:
> +- syscon-tcsr	Specifies TCSR handle, register offset, and bit position for
> +			configuring the phy mux setting.
> +
>  Optional clocks:
>    "iface"		System bus AXI clock.  Not present on all platforms
>    "sleep"		Sleep clock, used when USB3 core goes into low
> @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
>  
>  Example device nodes:
>  
> +		tcsr: syscon@1a400000 {
> +			compatible = "qcom,tcsr-ipq8064", "syscon";
> +			reg = <0x1a400000 0x100>;
> +		};
> +
>  		hs_phy: phy@100f8800 {
>  			compatible = "qcom,dwc3-hs-usb-phy";
>  			reg = <0x100f8800 0x30>;
> @@ -51,6 +60,8 @@ Example device nodes:
>  
>  			ranges;
>  
> +			syscon-tcsr = <&tcsr 0xb0 0x1>;
> +
>  			status = "ok";
>  
>  			dwc3@10000000 {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
> 
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Felipe Balbi Nov. 20, 2015, 3:08 p.m. UTC | #2
Hi,

Andy Gross <agross@codeaurora.org> writes:
> This patch adds documentation for the optional syscon-tcsr property in the
> Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
> configure the TCSR USB phy mux register.
>
> Signed-off-by: Andy Gross <agross@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> index ca164e7..dfa222d 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> @@ -8,6 +8,10 @@ Required properties:
>    "core"		Master/Core clock, have to be >= 125 MHz for SS
>  				operation and >= 60MHz for HS operation
>  
> +Optional properties:
> +- syscon-tcsr	Specifies TCSR handle, register offset, and bit position for
> +			configuring the phy mux setting.

oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue
layer then. By the time we reach dwc3, the mux should be properly
configured.

Kishon, any ideas ?
Andy Gross Nov. 20, 2015, 3:56 p.m. UTC | #3
On Fri, Nov 20, 2015 at 09:08:46AM -0600, Felipe Balbi wrote:
> 
> Hi,
> 
> Andy Gross <agross@codeaurora.org> writes:
> > This patch adds documentation for the optional syscon-tcsr property in the
> > Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
> > configure the TCSR USB phy mux register.
> >
> > Signed-off-by: Andy Gross <agross@codeaurora.org>
> > ---
> >  Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > index ca164e7..dfa222d 100644
> > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > @@ -8,6 +8,10 @@ Required properties:
> >    "core"		Master/Core clock, have to be >= 125 MHz for SS
> >  				operation and >= 60MHz for HS operation
> >  
> > +Optional properties:
> > +- syscon-tcsr	Specifies TCSR handle, register offset, and bit position for
> > +			configuring the phy mux setting.
> 
> oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue
> layer then. By the time we reach dwc3, the mux should be properly
> configured.
> 
> Kishon, any ideas ?
> 
> -- 
> balbi

The only issue with putting it at the phy layer is that i'd have redundant
syscon entries for each pair of phys, unless i group them somehow in dt.  The
only other issue I can think of is that in the downstream kernels, they do this
before messing with the configuration of the dwc3.  So long as the phys do their
thing before the dwc3 (phys latched before config), we're ok.
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
index ca164e7..dfa222d 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -8,6 +8,10 @@  Required properties:
   "core"		Master/Core clock, have to be >= 125 MHz for SS
 				operation and >= 60MHz for HS operation
 
+Optional properties:
+- syscon-tcsr	Specifies TCSR handle, register offset, and bit position for
+			configuring the phy mux setting.
+
 Optional clocks:
   "iface"		System bus AXI clock.  Not present on all platforms
   "sleep"		Sleep clock, used when USB3 core goes into low
@@ -22,6 +26,11 @@  Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
 
 Example device nodes:
 
+		tcsr: syscon@1a400000 {
+			compatible = "qcom,tcsr-ipq8064", "syscon";
+			reg = <0x1a400000 0x100>;
+		};
+
 		hs_phy: phy@100f8800 {
 			compatible = "qcom,dwc3-hs-usb-phy";
 			reg = <0x100f8800 0x30>;
@@ -51,6 +60,8 @@  Example device nodes:
 
 			ranges;
 
+			syscon-tcsr = <&tcsr 0xb0 0x1>;
+
 			status = "ok";
 
 			dwc3@10000000 {