From patchwork Tue Dec 1 09:14:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 7734441 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 72E399F1C2 for ; Tue, 1 Dec 2015 09:18:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9A10E206A9 for ; Tue, 1 Dec 2015 09:18:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99CF7206AD for ; Tue, 1 Dec 2015 09:18:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756057AbbLAJR4 (ORCPT ); Tue, 1 Dec 2015 04:17:56 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:35930 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755929AbbLAJQE (ORCPT ); Tue, 1 Dec 2015 04:16:04 -0500 Received: by wmww144 with SMTP id w144so163916160wmw.1 for ; Tue, 01 Dec 2015 01:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YZFIm4Zl81XopatedcskBtal1uS0tkPSxmkWXBhWG5E=; b=m8MlEQF4wGkopkv+PcThrVj39GjbK0da7F5kYdOa+Q+lo5J6DP0COdq2bkA2PvEAAf IXu7/M9KJPmxLQUAwvvmqhMqZkz5wIcclC0UxXapo4dH6/AFE5zUh4r/IlXS6lp4e+TP rvKy6Norj80ax/vdPMb9+2MwJEURnvUXESQdejIgCHwxbDtnn9l/mSbiHWsc8PdP2Io6 ZhncH/sZMJksiWn6/zZzm6CejK7mOX2bZEmV25TtDgaTKc0qC4P+GmXOrUHK8pdnkxVW 6epEWHtSP4jtrxBUAt34b1yCvjDbg4IIUb7w3Pm7Cx/j2b588N0voiFDXHH+e4bVA9Yu +jQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YZFIm4Zl81XopatedcskBtal1uS0tkPSxmkWXBhWG5E=; b=X1WpTwD2M691HOonlb9aNMwTbyCt1Yy0iwa6p1JnhHXazru3N+5piZDFvNmxNkF3KG zRStsl0k1zfX0W9zYoXpbvKQAHDBwUGwphkq475Pb7V6Eq0Ca+xly8jk4ehXsS3OizZV yQwmMZtjmQ6uVmPLTd7NZj4I0Df8RMh7JxyioFxGBxDWuz5bnSrg8vCKvlVzyIhNW1RL XVEiM39kjKM6OGAXV1oT0u76sqZARmZbVlEa1kLMa8EAKF8JGT/UySjjcuNRGjCV2Bhe K9Xr4RC/tgQRaQjHJ8K2z5DxY3t98KgfV/R9xXrWroyh3YN4ZOaHXM2KPe58q8A0c8jW 5Nmg== X-Gm-Message-State: ALoCoQk2zJWgvkj+do+RQiLFKdvLjTX+AmMv4TxINJpYLDppwErl8UHDSKlr4A149AWtob9TKZIb X-Received: by 10.28.142.205 with SMTP id q196mr36085619wmd.42.1448961363523; Tue, 01 Dec 2015 01:16:03 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id t64sm25290428wmf.23.2015.12.01.01.16.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Dec 2015 01:16:03 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul Cc: Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Andy Gross , Archit Taneja , Stanimir Varbanov Subject: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised Date: Tue, 1 Dec 2015 11:14:57 +0200 Message-Id: <1448961299-15161-3-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> References: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently we write BAM_IRQ_CLR register with zero even when no BAM_IRQ occured. This write has some bad side effects when the BAM instance is for the crypto engine. In case of crypto engine some of the BAM registers are xPU protected and they cannot be controlled by the driver. Signed-off-by: Stanimir Varbanov Reviewed-by: Andy Gross --- drivers/dma/qcom_bam_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index dc9da477eb69..0f06f3b7a72b 100644 --- a/drivers/dma/qcom_bam_dma.c +++ b/drivers/dma/qcom_bam_dma.c @@ -800,13 +800,17 @@ static irqreturn_t bam_dma_irq(int irq, void *data) if (srcs & P_IRQ) tasklet_schedule(&bdev->task); - if (srcs & BAM_IRQ) + if (srcs & BAM_IRQ) { clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); - /* don't allow reorder of the various accesses to the BAM registers */ - mb(); + /* + * don't allow reorder of the various accesses to the BAM + * registers + */ + mb(); - writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); + writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); + } return IRQ_HANDLED; }