From patchwork Wed Jan 13 05:56:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Mani X-Patchwork-Id: 8022221 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EC891BEEE5 for ; Wed, 13 Jan 2016 06:00:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CF2D92041A for ; Wed, 13 Jan 2016 06:00:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7495B20411 for ; Wed, 13 Jan 2016 06:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752369AbcAMGAi (ORCPT ); Wed, 13 Jan 2016 01:00:38 -0500 Received: from wolverine02.qualcomm.com ([199.106.114.251]:41580 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752037AbcAMGAh (ORCPT ); Wed, 13 Jan 2016 01:00:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qti.qualcomm.com; i=@qti.qualcomm.com; q=dns/txt; s=qcdkim; t=1452664836; x=1484200836; h=from:to:cc:subject:date:message-id:mime-version; bh=kJtKbkYliqjlcp1Et4PuxfdGv+Ygcrz5fBl5wmukwQA=; b=ziOCC2w3XC9Rb9eErAhESM0ye1nTqyAy7Ez08tnVQvn5zqTtrS/7rfpS ct94MudMhtfK2NVNlbtzHQgV+fXHsujVC29e1GcNFbzyvUOV5vjhOp+nB GPgIxq372686oIeJrtI3LtSQP/ZIVR3qnVdDArGkq+hzirnmE+4GKrEE5 4=; X-IronPort-AV: E=Sophos;i="5.22,287,1449561600"; d="scan'208";a="255439892" Received: from ironmsg03-r-new.qualcomm.com (HELO Ironmsg03-R.qualcomm.com) ([10.53.140.107]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 12 Jan 2016 22:00:36 -0800 X-IronPort-AV: E=McAfee;i="5700,7163,8042"; a="1066792490" Received: from nasanexm01c.na.qualcomm.com ([10.85.0.83]) by Ironmsg03-R.qualcomm.com with ESMTP/TLS/RC4-SHA; 12 Jan 2016 22:00:34 -0800 Received: from aphydexm01f.ap.qualcomm.com (10.252.127.15) by NASANEXM01C.na.qualcomm.com (10.85.0.83) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Tue, 12 Jan 2016 22:00:33 -0800 Received: from 10.80.81.91 (10.80.80.8) by aphydexm01f.ap.qualcomm.com (10.252.127.15) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 13 Jan 2016 11:27:56 +0530 Received: by 10.80.81.91 (sSMTP sendmail emulation); Wed, 13 Jan 2016 11:27:48 +0530 From: Raja Mani To: , CC: , , , , Raja Mani Subject: [PATCH v3] dt: bindings: add bindings for ipq4019 wifi block Date: Wed, 13 Jan 2016 11:26:44 +0530 Message-ID: <1452664604-8014-1-git-send-email-rmani@qti.qualcomm.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: NASANEXM01B.na.qualcomm.com (10.85.0.82) To aphydexm01f.ap.qualcomm.com (10.252.127.15) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree binding documentation details for wifi block present in Qualcomm IPQ4019 SoC into "qcom,ath10k.txt". Right now, ath10k wireless driver has support for PCI based wlan devices. There is a plan to extend ath10k driver to support wifi devices which are connected over AHB as well (enumeration will happen via device tree node). For AHB based devices (ie, ipq4019), all wifi properties are supplied via device tree (including irq, reg addr, cal data,etc). Signed-off-by: Raja Mani Acked-by: Rob Herring --- v3 changes: - Removed core-id - [Rob] - Documented which compatible string corresponds to pci devices and which corresponds to ahb devices. - [Rob] v2 changes: - Improved "core-id" description - [Rob] - Removed "status" documentation - [Rob] - Added description which properties are applicable for ahb and which are applicable for pci devices - [Rob] - Improved commit msg to explain the context. - Renamed "qca,msi_addr" to "qcom,msi_addr" and "qca,msi_base" to "qcom,msi_base" to follow uniformity. .../bindings/net/wireless/qcom,ath10k.txt | 89 ++++++++++++++++++++-- 1 file changed, 84 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index edefc26..bf8c0f8c 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -1,17 +1,46 @@ * Qualcomm Atheros ath10k wireless devices -For ath10k devices the calibration data can be provided through Device -Tree. The node is a child node of the PCI controller. - Required properties: --compatible : Should be "qcom,ath10k" +- compatible: Should be one of the following: + * "qcom,ath10k" + * "qcom,ipq4019-wifi" + +PCI based devices uses compatible string "qcom,ath10k" and takes only +calibration data via "qcom,ath10k-calibration-data". Reset of the properties +are not applicable for PCI based devices. + +AHB based devices (ie, ipq4019) uses compatible string "qcom,ipq4019-wifi" +and also uses most of the properties defined in this doc. Optional properties: +- reg: Address and length of the register set for the device. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reseti.txt for details. +- reset-names: Must include the list of following reset names, + "wifi_cpu_init" + "wifi_radio_srif" + "wifi_radio_warm" + "wifi_radio_cold" + "wifi_core_warm" + "wifi_core_cold" +- clocks: List of clock specifiers, must contain an entry for each required + entry in clock-names. +- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref", + "wifi_wcss_rtc". +- interrupts: List of interrupt lines. Must contain an entry + for each entry in the interrupt-names property. +- interrupt-names: Must include the entries for MSI interrupt + names ("msi0" to "msi15") and legacy interrupt + name ("legacy"), +- qcom,msi_addr: MSI interrupt address. +- qcom,msi_base: Base value to add before writing MSI data into + MSI address register. - qcom,ath10k-calibration-data : calibration data as an array, the length can vary between hw versions +Example (to supply the calibration data alone): -Example: +In this example, the node is defined as child node of the PCI controller. pci { pcie@0 { @@ -28,3 +57,53 @@ pci { }; }; }; + +Example (to supply ipq4019 SoC wifi block details): + +wifi0: wifi@a000000 { + compatible = "qcom,ipq4019-wifi"; + reg = <0xa000000 0x200000>; + resets = <&gcc WIFI0_CPU_INIT_RESET>, + <&gcc WIFI0_RADIO_SRIF_RESET>, + <&gcc WIFI0_RADIO_WARM_RESET>, + <&gcc WIFI0_RADIO_COLD_RESET>, + <&gcc WIFI0_CORE_WARM_RESET>, + <&gcc WIFI0_CORE_COLD_RESET>; + reset-names = "wifi_cpu_init", + "wifi_radio_srif", + "wifi_radio_warm", + "wifi_radio_cold", + "wifi_core_warm", + "wifi_core_cold"; + clocks = <&gcc GCC_WCSS2G_CLK>, + <&gcc GCC_WCSS2G_REF_CLK>, + <&gcc GCC_WCSS2G_RTC_CLK>; + clock-names = "wifi_wcss_cmd", + "wifi_wcss_ref", + "wifi_wcss_rtc"; + interrupts = <0 0x20 0x1>, + <0 0x21 0x1>, + <0 0x22 0x1>, + <0 0x23 0x1>, + <0 0x24 0x1>, + <0 0x25 0x1>, + <0 0x26 0x1>, + <0 0x27 0x1>, + <0 0x28 0x1>, + <0 0x29 0x1>, + <0 0x2a 0x1>, + <0 0x2b 0x1>, + <0 0x2c 0x1>, + <0 0x2d 0x1>, + <0 0x2e 0x1>, + <0 0x2f 0x1>, + <0 0xa8 0x0>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "legacy"; + qcom,msi_addr = <0x0b006040>; + qcom,msi_base = <0x40>; + qcom,ath10k-calibration-data = [ 01 02 03 ... ]; +};