From patchwork Wed Mar 23 22:05:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew McClintock X-Patchwork-Id: 8654891 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CADF4C0553 for ; Wed, 23 Mar 2016 22:08:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EA8D2203EB for ; Wed, 23 Mar 2016 22:08:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0905720411 for ; Wed, 23 Mar 2016 22:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755494AbcCWWGL (ORCPT ); Wed, 23 Mar 2016 18:06:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53336 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932536AbcCWWGH (ORCPT ); Wed, 23 Mar 2016 18:06:07 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 44D73615F1; Wed, 23 Mar 2016 22:06:01 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 13878615D7; Wed, 23 Mar 2016 22:06:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,HK_RANDOM_FROM, RCVD_IN_DNSWL_HI,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from mmcclint1-ubuntu.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mmcclint@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1B0C7615BC; Wed, 23 Mar 2016 22:06:00 +0000 (UTC) From: Matthew McClintock To: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org Cc: qca-upstream.external@qca.qualcomm.com, Matthew McClintock , Wim Van Sebroeck , Guenter Roeck , linux-watchdog@vger.kernel.org (open list:WATCHDOG DEVICE DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 08/17] watchdog: qcom: configure BARK time in addition to BITE time Date: Wed, 23 Mar 2016 17:05:03 -0500 Message-Id: <1458770712-10880-9-git-send-email-mmcclint@codeaurora.org> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> References: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For certain parts and some versions of TZ, TZ will reset the chip when a BARK is triggered even though it was not configured here. So by default let's configure this BARK time as well. Signed-off-by: Matthew McClintock Reviewed-by: Guenter Roeck --- drivers/watchdog/qcom-wdt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index e46f18d..53f57c3 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -22,18 +22,21 @@ enum wdt_reg { WDT_RST, WDT_EN, + WDT_BARK_TIME, WDT_BITE_TIME, }; static const u32 reg_offset_data_apcs_tmr[] = { [WDT_RST] = 0x38, [WDT_EN] = 0x40, + [WDT_BARK_TIME] = 0x4C, [WDT_BITE_TIME] = 0x5C, }; static const u32 reg_offset_data_kpss[] = { [WDT_RST] = 0x4, [WDT_EN] = 0x8, + [WDT_BARK_TIME] = 0x10, [WDT_BITE_TIME] = 0x14, }; @@ -62,6 +65,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd) writel(0, wdt_addr(wdt, WDT_EN)); writel(1, wdt_addr(wdt, WDT_RST)); + writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); writel(1, wdt_addr(wdt, WDT_EN)); return 0; @@ -104,6 +108,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, writel(0, wdt_addr(wdt, WDT_EN)); writel(1, wdt_addr(wdt, WDT_RST)); + writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); writel(1, wdt_addr(wdt, WDT_EN));