From patchwork Tue Jul 12 06:52:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9224661 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E682C60871 for ; Tue, 12 Jul 2016 06:53:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D86A027F7F for ; Tue, 12 Jul 2016 06:53:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD0C127F9A; Tue, 12 Jul 2016 06:53:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CB3527F7F for ; Tue, 12 Jul 2016 06:53:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753512AbcGLGxd (ORCPT ); Tue, 12 Jul 2016 02:53:33 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44335 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751384AbcGLGxc (ORCPT ); Tue, 12 Jul 2016 02:53:32 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9E99961295; Tue, 12 Jul 2016 06:53:31 +0000 (UTC) Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id EFF9E6127F; Tue, 12 Jul 2016 06:53:28 +0000 (UTC) From: Rajendra Nayak To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH 2/5] arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes Date: Tue, 12 Jul 2016 12:22:51 +0530 Message-Id: <1468306374-24153-3-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1468306374-24153-1-git-send-email-rnayak@codeaurora.org> References: <1468306374-24153-1-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP TSENS is part of GCC, hence add TSENS properties as part of GCC node. Also add thermal zones and qfprom nodes. Update GCC bindings doc to mention the possibility of optional TSENS properties that can be part of GCC node. Acked-by: Eduardo Valentin Signed-off-by: Rajendra Nayak --- .../devicetree/bindings/clock/qcom,gcc.txt | 18 ++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 119 +++++++++++++++++++++ 2 files changed, 137 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 9a60fde..16e2f84 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -23,6 +23,13 @@ Required properties : Optional properties : - #power-domain-cells : shall contain 1 +Optional properties: +- Qualcomm TSENS (thermal sensor device) on some devices can +be part of GCC and hence the TSENS properties can also be +part of the GCC/clock-controller node. +For more details on the TSENS properties please refer +Documentation/devicetree/bindings/thermal/qcom-tsens.txt + Example: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; @@ -31,3 +38,14 @@ Example: #reset-cells = <1>; #power-domain-cells = <1>; }; + +Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 906bb81..e54c215 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -86,6 +86,108 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 7>; + coefficients = <1199 0>; + + trips { + cpu_alert0: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip@1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + /* TODO: Add when cpufreq support is available */ + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 8>; + coefficients = <1132 0>; + + trips { + cpu_alert1: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip@1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + /* TODO: Add when cpufreq support is available */ + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 9>; + coefficients = <1199 0>; + + trips { + cpu_alert2: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip@1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + /* TODO: Add when cpufreq support is available */ + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 10>; + coefficients = <1132 0>; + + trips { + cpu_alert3: trip@0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip@1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + /* TODO: Add when cpufreq support is available */ + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; @@ -610,11 +712,28 @@ }; }; + qfprom: qfprom@00700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib { + reg = <0x414 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064"; reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #reset-cells = <1>; + #thermal-sensor-cells = <1>; }; lcc: clock-controller@28000000 {