From patchwork Thu Aug 11 08:40:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9274681 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 319EE60231 for ; Thu, 11 Aug 2016 08:47:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F56A2857D for ; Thu, 11 Aug 2016 08:47:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 13EA12857F; Thu, 11 Aug 2016 08:47:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AFD662857E for ; Thu, 11 Aug 2016 08:47:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932761AbcHKIog (ORCPT ); Thu, 11 Aug 2016 04:44:36 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57452 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752408AbcHKImS (ORCPT ); Thu, 11 Aug 2016 04:42:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3961D61367; Thu, 11 Aug 2016 08:41:26 +0000 (UTC) Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 43EB1612ED; Thu, 11 Aug 2016 08:41:22 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, tdas@codeaurora.org, Rajendra Nayak Subject: [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Date: Thu, 11 Aug 2016 14:10:52 +0530 Message-Id: <1470904858-11930-5-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1470904858-11930-1-git-send-email-rnayak@codeaurora.org> References: <1470904858-11930-1-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some PLLs can support an alpha mode, and a single alpha register (instead of registers to program the M/N values), the contents of which depend on the alpha mode selected. (They are either treated as two's complement or M/N value) Add support for this in the clk PLL driver. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/clk-pll.c | 8 ++++++-- drivers/clk/qcom/clk-pll.h | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c index 5b940d6..08d2fa2 100644 --- a/drivers/clk/qcom/clk-pll.c +++ b/drivers/clk/qcom/clk-pll.c @@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, u32 mask; regmap_write(regmap, pll->l_reg, config->l); - regmap_write(regmap, pll->m_reg, config->m); - regmap_write(regmap, pll->n_reg, config->n); + if (pll->alpha_reg) { + regmap_write(regmap, pll->alpha_reg, config->alpha); + } else { + regmap_write(regmap, pll->m_reg, config->m); + regmap_write(regmap, pll->n_reg, config->n); + } val = config->vco_val; val |= config->pre_div_val; diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h index ffd0c63..083727e 100644 --- a/drivers/clk/qcom/clk-pll.h +++ b/drivers/clk/qcom/clk-pll.h @@ -48,6 +48,7 @@ struct clk_pll { u32 l_reg; u32 m_reg; u32 n_reg; + u32 alpha_reg; u32 config_reg; u32 mode_reg; u32 status_reg; @@ -70,6 +71,7 @@ struct pll_config { u16 l; u32 m; u32 n; + u32 alpha; u32 vco_val; u32 vco_mask; u32 pre_div_val;