From patchwork Wed Sep 28 12:45:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Ramana X-Patchwork-Id: 9353803 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 179476077A for ; Wed, 28 Sep 2016 12:46:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0838029543 for ; Wed, 28 Sep 2016 12:46:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF6B029545; Wed, 28 Sep 2016 12:46:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BDD429543 for ; Wed, 28 Sep 2016 12:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932497AbcI1Mpw (ORCPT ); Wed, 28 Sep 2016 08:45:52 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59991 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932488AbcI1Mpt (ORCPT ); Wed, 28 Sep 2016 08:45:49 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 46B2761818; Wed, 28 Sep 2016 12:45:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475066747; bh=uwj1aaubtg/wBXDMUGJsQUaZW7InYMXFhkGp8/nzVNo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ty3Rbsz0x0GLc0AqU14x3n1TzrK4iEy9WFQIDPsftMkoFKdvO2y3Jvd2D2bS0GIZ5 +2ymTNZLSScO17NhVmuX3sEFo7i4k/ZlsnbNY8KN7xhG6Ad8+gLRN1fA20IdBN5Pql E7MPpsynCEjU/3CCv91uIK76L8MsCAAHUfjZtS+I= Received: from sramana-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sramana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9F10461803; Wed, 28 Sep 2016 12:45:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475066744; bh=uwj1aaubtg/wBXDMUGJsQUaZW7InYMXFhkGp8/nzVNo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ciz5AuyN7kYvgQQXp/HcGckqBkCDMW7DHVqK9nYwSaZcfILxXwDD5bNDetX9yQQBJ E6W2C5yAuulQ0rp6Gcr5I/m19kWfMgW7ehMg08PjZF8OHBSGoSp0g375pOEGCUX5TP WEirhMe25A9Fr0HyUk7tdxBQS5AMkzu5JbXPTGEE= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 9F10461803 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sramana@codeaurora.org From: Srinivas Ramana To: linux@armlinux.org.uk, nicolas.pitre@linaro.org, will.deacon@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srinivas Ramana Subject: [PATCH v1] ARM: decompressor: reset ttbcr fields to use TTBR0 on ARMv7 Date: Wed, 28 Sep 2016 18:15:28 +0530 Message-Id: <1475066728-27290-1-git-send-email-sramana@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <3441d0c3-c4b6-a795-a841-b61a8866ce17@arm.com> References: <3441d0c3-c4b6-a795-a841-b61a8866ce17@arm.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the bootloader uses the long descriptor format and jumps to kernel decompressor code, TTBCR may not be in a right state. Before enabling the MMU, it is required to clear the TTBCR.PD0 field to use TTBR0 for translation table walks. The commit dbece45894d3a ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores") does the reset of TTBCR.N, but doesn't consider all the bits for the size of TTBCR.N. Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to indicate the use of TTBR0 and the correct base address width. Fixes: dbece45894d3 ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores") Acked-by: Robin Murphy Signed-off-by: Srinivas Ramana --- arch/arm/boot/compressed/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index af11c2f8f3b7..fc6d541549a2 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -779,7 +779,7 @@ __armv7_mmu_cache_on: orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client bic r6, r6, #1 << 31 @ 32-bit translation system - bic r6, r6, #3 << 0 @ use only ttbr0 + bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control mcrne p15, 0, r6, c2, c0, 2 @ load ttb control