From patchwork Wed Oct 19 11:28:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9384339 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A46C4607D0 for ; Wed, 19 Oct 2016 15:10:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95DAA299E0 for ; Wed, 19 Oct 2016 15:10:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AD7629A14; Wed, 19 Oct 2016 15:10:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EE30299E0 for ; Wed, 19 Oct 2016 15:10:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S941335AbcJSPJZ (ORCPT ); Wed, 19 Oct 2016 11:09:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42692 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S944165AbcJSPGk (ORCPT ); Wed, 19 Oct 2016 11:06:40 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 32A0E61B03; Wed, 19 Oct 2016 11:29:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476876553; bh=Lcsod5C6Zuqe7FMn1/w0PCR3t7sdh+KnAasQLtKVZuQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j01SSUMnqHzxso6nu3tXxIn98uaBAJ3e77whSUfoTxFFoFOhyQQVyXrlGYHVNPlIo DGnmV4ccFdDfmwBVvlwGK5njT0Z6HgpPwu0Vkc5v2RL5oFMz3BHZYLLzGzXuYluy+A JG9Vj25nDeKmklEj7h3p4d16G1EiMZy8ySSY6f4Y= Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 563E161AF3; Wed, 19 Oct 2016 11:29:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476876552; bh=Lcsod5C6Zuqe7FMn1/w0PCR3t7sdh+KnAasQLtKVZuQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oxM3jdSea5w8fLZ/3M5v38Bdr/luOb4sR/lphSlJyBtGgZHz2lpgGidFJ+cbXXvcm 0jjOn8IHz/rTwWk3RUEVdP/8rbD/iiTai6P3kuCI1fwhR5IGZ5dYLC2iwHjRcycpo7 l2oT1FdeBgiWbcFeayOBgaEsBB9VWg0Viw1I2WQ0= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 563E161AF3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, tdas@codeaurora.org, Rajendra Nayak Subject: [PATCH 6/7] clk: qcom: Add force enable/disable needed for gfx3d rcg on msm8996 Date: Wed, 19 Oct 2016 16:58:42 +0530 Message-Id: <1476876523-27378-7-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1476876523-27378-1-git-send-email-rnayak@codeaurora.org> References: <1476876523-27378-1-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The gfx3d RCG on msm8996 needs to be force enabled/disabled by toggling the CMD_ROOT_EN bit. Add enable/disable ops to clk_gfx3d_ops Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/clk-rcg2.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index a071bba..6c79cca 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -300,7 +300,7 @@ static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, }; EXPORT_SYMBOL_GPL(clk_rcg2_ops); -static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +static int clk_rcg2_force_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const char *name = clk_hw_get_name(hw); @@ -316,20 +316,39 @@ static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) for (count = 500; count > 0; count--) { ret = clk_rcg2_is_enabled(hw); if (ret) - break; + return 0; udelay(1); } if (!count) pr_err("%s: RCG did not turn on\n", name); + return -ETIMEDOUT; +} + +static void clk_rcg2_force_disable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* clear force enable RCG */ + regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); +} + +static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +{ + int ret; + + ret = clk_rcg2_force_enable(hw); + if (ret) + return ret; + /* set clock rate */ ret = __clk_rcg2_set_rate(hw, rate); if (ret) return ret; - /* clear force enable RCG */ - return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, - CMD_ROOT_EN, 0); + clk_rcg2_force_disable(hw); + return 0; } static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, @@ -801,6 +820,8 @@ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_gfx3d_ops = { + .enable = clk_rcg2_force_enable, + .disable = clk_rcg2_force_disable, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent,