From patchwork Fri Nov 4 22:44:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9413473 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DE6DD60724 for ; Fri, 4 Nov 2016 22:45:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF9042B295 for ; Fri, 4 Nov 2016 22:45:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BAEB02B298; Fri, 4 Nov 2016 22:45:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 610F82B299 for ; Fri, 4 Nov 2016 22:45:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757266AbcKDWpV (ORCPT ); Fri, 4 Nov 2016 18:45:21 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55374 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762166AbcKDWpR (ORCPT ); Fri, 4 Nov 2016 18:45:17 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B9F196135C; Fri, 4 Nov 2016 22:45:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1478299516; bh=uJEIXJp6Ja+1Ykm/6Jfvs5DOFrqNwTsEIE+nB7qa5pY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C++Nxm2JCG+n4TdjdEiUVpXGwFdf7aGjot6rLZ5SlUIZuqs+CiOXddDHQPDWjLrXR BsjIn7p5QNVatwURHhIjHsPTLOA5C0N/DActA99x725X6nAc8BWQRLZ3D+2R2S0lQz g+ItZODoRWK3+nSeXJHBgq4MS8EAUb3Ml82d7THY= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3EED4613F9; Fri, 4 Nov 2016 22:45:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1478299515; bh=uJEIXJp6Ja+1Ykm/6Jfvs5DOFrqNwTsEIE+nB7qa5pY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aOBqyEGPstZSuqbodbf1IMUD/MvifXLs2kQ6AFa1ILWYG4cFLUX2lHKXs3v9yS/Gu +9YNY5LYJMvKWVH4B6finEatGXLQ5dclnezXgpZcZoXGwbNqLXoZF/uyxrVkjKA73A gujPSqrp7i89fyL7SYnQNYFv8a0U5Logm/q3YoiQ= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 3EED4613F9 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH 11/16] arm64: dts: Add Adreno GPU and GPU smmu definitions Date: Fri, 4 Nov 2016 16:44:52 -0600 Message-Id: <1478299497-9729-12-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478299497-9729-1-git-send-email-jcrouse@codeaurora.org> References: <1478299497-9729-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an initial node for the Adreno GPU and it's companion SMMU. The GPU node is mostly complete except for a bare bones power table that will be filled out more completely later. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1f7f8a9..f71b468 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -467,6 +467,84 @@ }; }; + adreno_smmu: arm,smmu@b40000 { + compatible = "arm,smmu-v2"; + reg = <0xb40000 0x10000>; + + #global-interrupts = <1>; + interrupts = <0 334 0>, + <0 329 0>, + <0 330 0>; + #iommu-cells = <1>; + + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc MMSS_MMAGIC_CFG_AHB_CLK>, + <&mmcc GPU_AHB_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mmagic_ahb_clk", + "mmagic_cfg_ahb_clk", + "gpu_ahb_clk", + "gcc_mmss_bimc_gfx_clk", + "gcc_bimc_gfx_clk", + "mmss_misc_bus_clk"; + + power-domains = <&mmcc GPU_GDSC>; + + qcom,skip-init; + qcom,register-save; + + status = "okay"; + }; + + adreno-3xx@b00000 { + compatible = "qcom,adreno-3xx"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>, + <&mmcc MMSS_MMAGIC_AHB_CLK>; + + clock-names = "core_clk", + "iface_clk", + "rbbmtimer_clk", + "mem_clk", + "mem_iface_clk", + "alt_mem_iface_clk"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + /* There are patchlevel 3 chips in the world (Snapdragon + * (820) but they are functionally similar to the 821 in + * the code so we can safely set the chipset as + * patchlevel 4. */ + qcom,chipid = <0x05030004>; + + /* This is a safe speed for bring up in all bin levels. + * This isn't the fastest the chip can go, but we can + * get there eventually */ + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <205000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + mdp_smmu: arm,smmu@d00000 { compatible = "arm,smmu-v2"; reg = <0xd00000 0x10000>;