From patchwork Mon Nov 14 11:00:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9427211 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 62CB560756 for ; Mon, 14 Nov 2016 11:01:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5385F28841 for ; Mon, 14 Nov 2016 11:01:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4831F2884D; Mon, 14 Nov 2016 11:01:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8D4B28850 for ; Mon, 14 Nov 2016 11:01:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933913AbcKNLB1 (ORCPT ); Mon, 14 Nov 2016 06:01:27 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:60302 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933759AbcKNLBB (ORCPT ); Mon, 14 Nov 2016 06:01:01 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 048CE61573; Mon, 14 Nov 2016 11:01:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479121261; bh=9s03r7k4yfnHDhw+NfwIqhpHbFrugb6fgl1sbJoBt7I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4EoB5/0zcNbF2nXdhbPJ8tszEUWNQGTkxwKJbUnd/Kj/8Q4w1+pYUh7wthKE34st 3JnjzE2P8cybIlsoayzXE0nNV6YLlwi6sagbHWhLHgutHhyXiIj5WPSAQ4POmoQtlT h/RF3DUiyaxVjzS1LQNnqg9KrDHsWuiyBNaINnsM= Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A3265611DE; Mon, 14 Nov 2016 11:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479121260; bh=9s03r7k4yfnHDhw+NfwIqhpHbFrugb6fgl1sbJoBt7I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YTpkaXiZEFIYavQy6ShaAw4c+WxlJXV6zp9s/8ssQM5vlJfyo5z7JHfxV4TNHVYDa EWsf6UpGeh2XR1DsGK+IVPFCBCmvwMfLdOTzQ/V8lBQ8MP3fdyZQesb6vyzqTJz/pe Hig9Ucwo8UQ1J64ODozRDuQ5Iw1ExKRJv6ihUEUA= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org A3265611DE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, tdas@codeaurora.org, Rajendra Nayak Subject: [PATCH v4 2/3] clk: qcom: support dynamic update using latched interface Date: Mon, 14 Nov 2016 16:30:39 +0530 Message-Id: <1479121240-20922-3-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1479121240-20922-1-git-send-email-rnayak@codeaurora.org> References: <1479121240-20922-1-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Taniya Das Alpha PLLs can support 2 kinds of input signals, normal and latched. The normal input is directly passed to the core, while the latched input requires a latch and acknowledge sequence to be performed for the changed input to propagate. Alpha PLLs can support dynamic update with both kind of input signals. The ones which support this using a latched interface however need to follow the latch/wait-for-ack sequence to be performed when the rate changes. Mark these with a new flag 'SUPPORTS_LATCHED_INPUT' to handle this as part of clk_alpha_pll_set_rate() Signed-off-by: Rajendra Nayak Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 37 ++++++++++++++++++++++++++++++++++++- drivers/clk/qcom/clk-alpha-pll.h | 5 +++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index ecb9e7f..15703b4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -32,6 +32,7 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) # define PLL_OFFLINE_ACK BIT(28) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) @@ -48,6 +49,7 @@ # define PLL_VCO_MASK 0x3 #define PLL_USER_CTL_U 0x14 +# define PLL_LATCH_INTERFACE BIT(11) #define PLL_CONFIG_CTL 0x18 #define PLL_CONFIG_CTL_U 0x20 @@ -109,6 +111,10 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_latch_ack(pll) \ + wait_for_pll(pll, BIT(pll->latch_ack_bit), pll->latch_ack_inverse, \ + "latch ack") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { @@ -140,6 +146,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, if (pll->flags & SUPPORTS_FSM_MODE) qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0); + + if (pll->flags & SUPPORTS_LATCHED_INPUT) + regmap_update_bits(regmap, off + PLL_USER_CTL_U, + PLL_LATCH_INTERFACE, 0); } static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) @@ -376,6 +386,27 @@ static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a) return alpha_pll_calc_rate(prate, l, a); } +static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) +{ + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, + PLL_UPDATE, PLL_UPDATE); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + wait_for_pll_latch_ack(pll); + + /* Return latch input to 0 */ + regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, + PLL_UPDATE, 0); + + /* Wait for PLL output to stabilize */ + udelay(100); + + return 0; +} + static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, int (*enable)(struct clk_hw *hw), @@ -431,8 +462,12 @@ static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN, PLL_ALPHA_EN); - if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled) + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE) { + if (pll->flags & SUPPORTS_LATCHED_INPUT) + clk_alpha_pll_update_latch(pll); + } else if (enabled) { enable(hw); + } return 0; } diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 7aaa11c..c580d20 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,8 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @vco_table: array of VCO settings + * @latch_ack_bit: Bit to check for latch acknowledge + * @latch_ack_inverse: Bit set to 0 signifies an ack * @min_rate: Minimim rate for PLLs with single VCO range * @max_rate: Maximun rate for PLLs with single VCO range * @clkr: regmap clock handle @@ -40,7 +42,10 @@ struct clk_alpha_pll { #define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) #define SUPPORTS_DYNAMIC_UPDATE BIT(3) +#define SUPPORTS_LATCHED_INPUT BIT(4) u8 flags; + u8 latch_ack_bit; + bool latch_ack_inverse; unsigned long min_rate; unsigned long max_rate;