From patchwork Wed Nov 16 17:01:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dwivedi, Avaneesh Kumar (avani)" X-Patchwork-Id: 9432215 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 005CE60755 for ; Wed, 16 Nov 2016 17:02:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E395128F71 for ; Wed, 16 Nov 2016 17:02:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D85FE28FCB; Wed, 16 Nov 2016 17:02:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5221F28FCC for ; Wed, 16 Nov 2016 17:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752492AbcKPRCI (ORCPT ); Wed, 16 Nov 2016 12:02:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:57462 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932469AbcKPRCF (ORCPT ); Wed, 16 Nov 2016 12:02:05 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9406D61515; Wed, 16 Nov 2016 17:02:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479315724; bh=xc21RweR0UAG5ozHkyWqhEMOIQ6C6+2RogV/4yNUlsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H8jEE6gUWPpKLKFLifZgn88XOhCCDWucxaU+/1XsHoEyUUDkPNbdVPnpgYR38U/qR Bzfr6aEU4uJ+JQOIC854sOrrcEI2xBH9ZUrT8ra+vde6jM5NntgSBWg6fi8WAQz+Ot bMbKXgU6vUOr2tw+bpr8104/BgzBNr8dGKnckdUY= Received: from akdwived-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akdwived@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AAB556151D; Wed, 16 Nov 2016 17:02:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479315723; bh=xc21RweR0UAG5ozHkyWqhEMOIQ6C6+2RogV/4yNUlsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mgv169vc/xDSj0VTlKLZD6UAy6sYeWV4BPfVhoXx6RBvwKUZaTNN5tSEmfbzMO1zQ X0ZMXyDO95nOapn7rf99Z1f/+1J8WKO5UlBcwpagvT/t3PKRtefHYLeOKelZxD0elh SJgphYk3HECClHVGHnxpBmVa7UogLfU7pgyEhRv8= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org AAB556151D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=akdwived@codeaurora.org From: Avaneesh Kumar Dwivedi To: bjorn.andersson@linaro.org Cc: sboyd@codeaurora.org, agross@codeaurora.org, linux-arm-msm@vger.kernel.org, Avaneesh Kumar Dwivedi Subject: [PATCH v4 06/10] remoteproc: qcom: Modify clock enable and disable routine Date: Wed, 16 Nov 2016 22:31:32 +0530 Message-Id: <1479315696-15490-7-git-send-email-akdwived@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479315696-15490-1-git-send-email-akdwived@codeaurora.org> References: <1479315696-15490-1-git-send-email-akdwived@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Clock handling is made generic than need to add new clock every time when required to support new hexagon version. also where ever required invoking clock enable disable routine is replaced by this new prototype. Also clock disable interface is separated out into two separate routine to handle proxy clock alone unvoting when handover interrupt is arrived. Signed-off-by: Avaneesh Kumar Dwivedi --- drivers/remoteproc/qcom_q6v5_pil.c | 90 +++++++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 25 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c index 57c67e1..fe7c409 100644 --- a/drivers/remoteproc/qcom_q6v5_pil.c +++ b/drivers/remoteproc/qcom_q6v5_pil.c @@ -127,10 +127,6 @@ struct q6v5 { struct qcom_smem_state *state; unsigned stop_bit; - - struct clk *ahb_clk; - struct clk *axi_clk; - struct clk *rom_clk; struct clk **active_clks; struct clk **proxy_clks; struct reg_info *active_regs; @@ -293,6 +289,52 @@ static void q6v5_regulator_disable(struct q6v5 *qproc) q6v5_active_regulator_disable(qproc); } +static int q6v5_clk_enable(struct device *dev, struct clk **clks, + int clk_count) +{ + int rc = 0; + int i; + + for (i = 0; i < clk_count; i++) { + rc = clk_prepare_enable(clks[i]); + if (rc) { + dev_err(dev, "Clock enable failed\n"); + goto err; + } + } + + return 0; +err: + for (i--; i >= 0; i--) + clk_disable_unprepare(clks[i]); + + return rc; +} + +static void q6v5_proxy_clk_disable(struct q6v5 *qproc) +{ + int i; + struct clk **clks = qproc->proxy_clks; + + for (i = 0; i < qproc->proxy_clk_count; i++) + clk_disable_unprepare(clks[i]); +} + +static void q6v5_active_clk_disable(struct q6v5 *qproc) +{ + int i; + struct clk **clks = qproc->proxy_clks; + + for (i = 0; i < qproc->proxy_clk_count; i++) + clk_disable_unprepare(clks[i]); +} + +static void q6v5_clk_disable(struct q6v5 *qproc) +{ + q6v5_proxy_clk_disable(qproc); + q6v5_active_clk_disable(qproc); +} + static int q6v5_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5 *qproc = rproc->priv; @@ -589,6 +631,13 @@ static int q6v5_start(struct rproc *rproc) return ret; } + ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, + qproc->proxy_clk_count); + if (ret) { + dev_err(qproc->dev, "failed to enable proxy clocks\n"); + goto disable_proxy_reg; + } + ret = q6v5_regulator_enable(qproc, qproc->active_regs, qproc->active_reg_count); if (ret) { @@ -601,17 +650,12 @@ static int q6v5_start(struct rproc *rproc) goto disable_vdd; } - ret = clk_prepare_enable(qproc->ahb_clk); - if (ret) + ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, + qproc->active_clk_count); + if (ret) { + dev_err(qproc->dev, "failed to enable clocks\n"); goto assert_reset; - - ret = clk_prepare_enable(qproc->axi_clk); - if (ret) - goto disable_ahb_clk; - - ret = clk_prepare_enable(qproc->rom_clk); - if (ret) - goto disable_axi_clk; + } writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); @@ -646,25 +690,23 @@ static int q6v5_start(struct rproc *rproc) qproc->running = true; - /* TODO: All done, release the handover resources */ - + q6v5_proxy_clk_disable(qproc); + q6v5_proxy_regulator_disable(qproc); return 0; halt_axi_ports: q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); - - clk_disable_unprepare(qproc->rom_clk); -disable_axi_clk: - clk_disable_unprepare(qproc->axi_clk); -disable_ahb_clk: - clk_disable_unprepare(qproc->ahb_clk); + q6v5_active_clk_disable(qproc); assert_reset: reset_control_assert(qproc->mss_restart); disable_vdd: q6v5_active_regulator_disable(qproc); disable_proxy_clk: + q6v5_proxy_clk_disable(qproc); +disable_proxy_reg: + q6v5_proxy_regulator_disable(qproc); return ret; } @@ -690,9 +732,7 @@ static int q6v5_stop(struct rproc *rproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); reset_control_assert(qproc->mss_restart); - clk_disable_unprepare(qproc->rom_clk); - clk_disable_unprepare(qproc->axi_clk); - clk_disable_unprepare(qproc->ahb_clk); + q6v5_clk_disable(qproc); q6v5_regulator_disable(qproc); return 0;