From patchwork Wed Nov 16 17:01:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dwivedi, Avaneesh Kumar (avani)" X-Patchwork-Id: 9432217 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 74BA960476 for ; Wed, 16 Nov 2016 17:02:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63EAC28F71 for ; Wed, 16 Nov 2016 17:02:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 572FB28FC9; Wed, 16 Nov 2016 17:02:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D386828F71 for ; Wed, 16 Nov 2016 17:02:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932469AbcKPRCM (ORCPT ); Wed, 16 Nov 2016 12:02:12 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:57636 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932811AbcKPRCJ (ORCPT ); Wed, 16 Nov 2016 12:02:09 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 76E9F61564; Wed, 16 Nov 2016 17:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479315728; bh=vM7Rbo9f+3QfzXmUbUHxMlGj/VLgZVvA69d2pyyHgFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NT/PFwMvzfymK1Ja/E0JrskmJhHR1f3F21BO7jDONIWUmkSfOMVW0NGzSstMUBEZf e7rB96t+n7WDKvfYd9nBIaupcKd6Q08Y7i22ytXBOJei0yk//cYx4j5Cp2y+K9+NRZ 0oSpvLLY5jUb782z/SSI8xJETpg1gELRTXxtnp+Q= Received: from akdwived-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akdwived@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5124B61503; Wed, 16 Nov 2016 17:02:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479315726; bh=vM7Rbo9f+3QfzXmUbUHxMlGj/VLgZVvA69d2pyyHgFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KnKS2heVq3BDe1uZF05Ku8fq7xJdxdqA4Oiej98JiZR8Y73rR9PaI6K+MLsKtmvBA YKsn/VYTueKCYvAl/Yiy7fCSVvefWOSpNgtC/vTBrjtiZMaPuQ3DgDzSEHU7AyXkIM 8QuT1MroJxOGMZQ3MKitsuLEGuq74TPoRxmWCWUE= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 5124B61503 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=akdwived@codeaurora.org From: Avaneesh Kumar Dwivedi To: bjorn.andersson@linaro.org Cc: sboyd@codeaurora.org, agross@codeaurora.org, linux-arm-msm@vger.kernel.org, Avaneesh Kumar Dwivedi Subject: [PATCH v4 07/10] remoteproc: qcom: Add new routine for mss restart programming Date: Wed, 16 Nov 2016 22:31:33 +0530 Message-Id: <1479315696-15490-8-git-send-email-akdwived@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479315696-15490-1-git-send-email-akdwived@codeaurora.org> References: <1479315696-15490-1-git-send-email-akdwived@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MSS restart is done via reset controller, but on certain hexagon version clock reset controller interface can not be utilized as MSS restart register is not a block control reset which are supported via clock reset control framework. In this case restart register is programmed directly by register programming through ioremap. Signed-off-by: Avaneesh Kumar Dwivedi --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 +++ drivers/remoteproc/qcom_q6v5_pil.c | 35 ++++++++++++++++++---- 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index cbc165c..717bd4a 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -79,6 +79,10 @@ on the Qualcomm Hexagon core. Definition: a phandle reference to a syscon representing TCSR followed by the three offsets within syscon for q6, modem and nc halt registers. +- qcom,qdsp6v56-1-5: + Usage: required + Value type: boolean + Definition: Present if the qdsp version is v56 1.5 = SUBNODES: The Hexagon node must contain two subnodes, named "mba" and "mpss" representing diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c index fe7c409..77a69eb 100644 --- a/drivers/remoteproc/qcom_q6v5_pil.c +++ b/drivers/remoteproc/qcom_q6v5_pil.c @@ -148,6 +148,8 @@ struct q6v5 { phys_addr_t mpss_reloc; void *mpss_region; size_t mpss_size; + + bool qdsp6v56_1_5; }; @@ -335,6 +337,14 @@ static void q6v5_clk_disable(struct q6v5 *qproc) q6v5_active_clk_disable(qproc); } +static void pil_mss_restart_reg(struct q6v5 *qproc, u32 mss_restart) +{ + if (qproc->restart_reg) { + writel_relaxed(mss_restart, qproc->restart_reg); + udelay(2); + } +} + static int q6v5_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5 *qproc = rproc->priv; @@ -644,10 +654,15 @@ static int q6v5_start(struct rproc *rproc) dev_err(qproc->dev, "failed to enable supplies\n"); goto disable_proxy_clk; } - ret = reset_control_deassert(qproc->mss_restart); - if (ret) { - dev_err(qproc->dev, "failed to deassert mss restart\n"); + + if (qproc->qdsp6v56_1_5) + pil_mss_restart_reg(qproc, 0); + else { + ret = reset_control_deassert(qproc->mss_restart); + if (ret) { + dev_err(qproc->dev, "failed to deassert mss restart\n"); goto disable_vdd; + } } ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, @@ -700,7 +715,8 @@ static int q6v5_start(struct rproc *rproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); q6v5_active_clk_disable(qproc); assert_reset: - reset_control_assert(qproc->mss_restart); + if (qproc->qdsp6v56_1_5) + reset_control_assert(qproc->mss_restart); disable_vdd: q6v5_active_regulator_disable(qproc); disable_proxy_clk: @@ -731,7 +747,13 @@ static int q6v5_stop(struct rproc *rproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); - reset_control_assert(qproc->mss_restart); + if (qproc->qdsp6v56_1_5) + pil_mss_restart_reg(qproc, 1); + else { + ret = reset_control_assert(qproc->mss_restart); + if (ret) + dev_err(qproc->dev, "failed to deassert mss restart\n"); + } q6v5_clk_disable(qproc); q6v5_regulator_disable(qproc); @@ -1063,6 +1085,9 @@ static int q6v5_probe(struct platform_device *pdev) } qproc->active_reg_count = count; + qproc->qdsp6v56_1_5 = of_property_read_bool(pdev->dev.of_node, + "qcom,qdsp6v56-1-5"); + ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt); if (ret < 0) goto free_rproc;