From patchwork Tue Nov 22 12:02:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 9440887 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AFACB60235 for ; Tue, 22 Nov 2016 12:03:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A55E52851B for ; Tue, 22 Nov 2016 12:03:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A87028520; Tue, 22 Nov 2016 12:03:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 02A392851B for ; Tue, 22 Nov 2016 12:03:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932469AbcKVMDX (ORCPT ); Tue, 22 Nov 2016 07:03:23 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:47390 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755437AbcKVMDK (ORCPT ); Tue, 22 Nov 2016 07:03:10 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8B856614EA; Tue, 22 Nov 2016 12:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479816189; bh=5H4lobXGFRnwbfP86LtLk2jjiIgcOLPlpLh70Cu243g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QUWj5+l+CGts20Fbt42MrfY2nC37MqGWxVLb0S/gBk6g+Jl80k6+f1vWl4NttX/SA TXRcmuZbid9FtKaXbdwCj047r9AKGFm3RDsk90OwWI44CeGZzF0lAVq944/KO47Md/ ajaV34G02LZtFmeiucKibojpVv5R9uTWDJAKY8PY= Received: from blr-ubuntu-41.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E5136614EA; Tue, 22 Nov 2016 12:03:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479816188; bh=5H4lobXGFRnwbfP86LtLk2jjiIgcOLPlpLh70Cu243g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V5GbAhBXaq27p3cBeNoQl5g5acEpFFSnjOwLuaLbAe4qRpbUow9rfyjm7sIwha0R6 Kt08XXCvGNYqEgNWXqWDXHGpNLCO93A/xAtHrpE7AepvE84k8nb6YrHBWwTP0rkos8 4GxxApnSvkpvoLV575fmZ1CMVN/f9Wijj9NhFJbs= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org E5136614EA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: srinivas.kandagatla@linaro.org, sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org, Vivek Gautam Subject: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Date: Tue, 22 Nov 2016 17:32:42 +0530 Message-Id: <1479816163-5260-4-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> References: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Qualcomm chipsets have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Adding dt binding information for the same. Signed-off-by: Vivek Gautam Acked-by: Rob Herring --- Changes since v1: - New patch, forked out of the original driver patch: "phy: qcom-qmp: new qmp phy driver for qcom-chipsets" - updated bindings to include mem resource as a list of offset - length pair for serdes block and for each lane. - added a new binding for 'lane-offsets' that contains offsets to tx, rx and pcs blocks from each lane base address. .../devicetree/bindings/phy/qcom-qmp-phy.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt new file mode 100644 index 0000000..ffb173b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -0,0 +1,74 @@ +Qualcomm QMP PHY +---------------- + +QMP phy controller supports physical layer functionality for a number of +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +Required properties: + - compatible: compatible list, contains: + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. + - reg: list of offset and length pair of the PHY register sets. + at index 0: offset and length of register set for PHY common + serdes block. + from index 1 - N: offset and length of register set for each lane, + for N number of phy lanes (ports). + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes. + - #phy-cells: must be 1 + - Cell after phy phandle should be the port (lane) number. + - clocks: a list of phandles and clock-specifier pairs, + one for each entry in clock-names. + - clock-names: must be "cfg_ahb" for phy config clock, + "aux" for phy aux clock, + "ref_clk" for 19.2 MHz ref clk, + "ref_clk_src" for reference clock source, + "pipe" for pipe clock specific to + each port/lane (Optional). + - resets: a list of phandles and reset controller specifier pairs, + one for each entry in reset-names. + - reset-names: must be "phy" for reset of phy block, + "common" for phy common block reset, + "cfg" for phy's ahb cfg block reset (Optional). + "port" for reset specific to + each port/lane (Optional). + - vdda-phy-supply: Phandle to a regulator supply to PHY core block. + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. + +Optional properties: + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk + pll block. + +Example: + pcie_phy: pciephy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x034000 0x48f>, + <0x035000 0x5bf>, + <0x036000 0x5bf>, + <0x037000 0x5bf>; + /* tx, rx, pcs */ + lane-offsets = <0x0 0x200 0x400>; + #phy-cells = <1>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&rpmcc MSM8996_RPM_SMD_LN_BB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", + "ref_clk_src", "ref_clk", + "pipe0", "pipe1", "pipe2"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "phy", "common", "cfg", + "lane0", "lane1", "lane2"; + };