From patchwork Mon Nov 28 19:28:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9450069 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 466F56074E for ; Mon, 28 Nov 2016 19:28:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 363FD27FB3 for ; Mon, 28 Nov 2016 19:28:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B59527FE4; Mon, 28 Nov 2016 19:28:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6ADE27FB3 for ; Mon, 28 Nov 2016 19:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754596AbcK1T2z (ORCPT ); Mon, 28 Nov 2016 14:28:55 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45484 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754146AbcK1T2x (ORCPT ); Mon, 28 Nov 2016 14:28:53 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1F1CE613B0; Mon, 28 Nov 2016 19:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1480361333; bh=4IZQ1gRn96jIOUfwL4UjF6fHVbt6PDYrZ8tXI/xlNaY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nwF82x6OslAPE4RkA/TLtcTsj35n0tM0wWoNU/eWEWZzHdb8FnTXMTBzd/QJQerCe Cb3Llshw88uonkgZFGum10CTKt0X5JdABInctZ4njm5mRfhSjl15zWnPQ2/vb1U83R iPcbjCam2XopNVzEJK0KQse7RA/G5ptA2HwrKMGs= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6520F613B0; Mon, 28 Nov 2016 19:28:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1480361332; bh=4IZQ1gRn96jIOUfwL4UjF6fHVbt6PDYrZ8tXI/xlNaY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OLyM4wB4+t5L0wOrSSHesG2FbxQUJ5K4jOTNC8QXdgP2D6b1hTNt5RWVNqBGxSC/e YazG/lR2WzL0gOYD5+RN7ndGvmZhF5SvC7YssVagJhubKMHPIyv/0m3hKufvP5KDb9 qusDQA1LfBqmUxzvesEoUSjD0YJudtxQrOQkwZw0= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 6520F613B0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume() Date: Mon, 28 Nov 2016 12:28:35 -0700 Message-Id: <1480361317-9937-11-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480361317-9937-1-git-send-email-jcrouse@codeaurora.org> References: <1480361317-9937-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an interface to trigger the remote processor to reinitialize the GPU zap shader on power-up. Signed-off-by: Jordan Crouse --- drivers/firmware/qcom_scm-32.c | 5 +++++ drivers/firmware/qcom_scm-64.c | 15 +++++++++++++++ drivers/firmware/qcom_scm.c | 6 ++++++ drivers/firmware/qcom_scm.h | 2 ++ include/linux/qcom_scm.h | 2 ++ 5 files changed, 30 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c6aeedb..1a0876c 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -560,3 +560,8 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : le32_to_cpu(out); } + +int __qcom_scm_gpu_zap_resume(struct device *dev) +{ + return -ENOTSUPP; +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index cdf422f2..82aba97 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -363,3 +363,18 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : res.a1; } + +int __qcom_scm_gpu_zap_resume(struct device *dev) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = 0; + desc.args[1] = 13; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, 0x0A, &desc, &res); + + return ret ? : res.a1; +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 143edbc..e26c7f4 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -312,6 +312,12 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = { .deassert = qcom_scm_pas_reset_deassert, }; +int qcom_scm_gpu_zap_resume(void) +{ + return __qcom_scm_gpu_zap_resume(__scm->dev); +} +EXPORT_SYMBOL(qcom_scm_gpu_zap_resume); + /** * qcom_scm_is_available() - Checks if SCM is available */ diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 3584b00..581f934 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -56,6 +56,8 @@ extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral); extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral); extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset); +extern int __qcom_scm_gpu_zap_resume(struct device *dev); + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index cc32ab8..e1729fb 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -37,6 +37,8 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); +extern int qcom_scm_gpu_zap_resume(void); + #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1