From patchwork Mon Nov 28 19:28:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9450075 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D1666074E for ; Mon, 28 Nov 2016 19:29:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F007B27FBE for ; Mon, 28 Nov 2016 19:28:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E51FA28047; Mon, 28 Nov 2016 19:28:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7972527FBE for ; Mon, 28 Nov 2016 19:28:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754591AbcK1T26 (ORCPT ); Mon, 28 Nov 2016 14:28:58 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45980 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752169AbcK1T2z (ORCPT ); Mon, 28 Nov 2016 14:28:55 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7DA38613FD; Mon, 28 Nov 2016 19:28:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1480361334; bh=q02q0y2GJB3GbJeEVM8BRV0Ezaq0wX1jNs/VN8Rjo2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lkPMgCSw6KvzdKnfduxBww1hHR5JIKoueZ6grzQhLq0c+qtSztpuhsjCLSvb9ZYuL NJ4JroFFptEwgTav6donm2vXR/1Puc361pHGdQ6ytbCz6GwhGwZeHHapgXzMaY7GME SaIk8eURrgjgWM/Op+aP1KaMlg9+NBIqZzHV3zl4= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6F5FE613E7; Mon, 28 Nov 2016 19:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1480361333; bh=q02q0y2GJB3GbJeEVM8BRV0Ezaq0wX1jNs/VN8Rjo2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C43GCd2gGnY22qIGucdoVdTQnl8UZUh4OfhdplluAjXva78Qrbymor8ulgVfSVG2H ourQttTOAt5moXpgYdt3/1gyLhv5NpCyN+r8NCvfhKCg1EHxYN0IQoa6WGtJbGr38+ z4k2seetLL+AyP652mVH0PNFQGlNHSN8fN1GfqoI= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 6F5FE613E7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can Date: Mon, 28 Nov 2016 12:28:37 -0700 Message-Id: <1480361317-9937-13-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480361317-9937-1-git-send-email-jcrouse@codeaurora.org> References: <1480361317-9937-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The A5XX GPU powers on in "secure" mode. In secure mode the GPU can only render to buffers that are marked as secure and inaccessible to the kernel and user through a series of hardware protections. In practice secure mode is used to draw things like a UI on a secure video frame. In order to switch out of secure mode the GPU executes a special shader that clears out the GMEM and other sensitve registers and then writes a register. Because the kernel can't be trusted the shader binary is signed and verified and programmed by the secure world. To do this we need to read the MDT header and the segments from the firmware location and put them in memory and present them for approval. For targets without secure support there is an out: if the secure world doesn't support secure then there are no hardware protections and we can freely write the SECVID_TRUST register from the CPU. We don't have 100% confidence that we can query the secure capabilities at run time but we have enough calls that need to go right to give us some confidence that we're at least doing something useful. Of course if we guess wrong you trigger a permissions violation which usually ends up in a system crash but thats a problem that shows up immediately. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 72 ++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index eefe197..a7a58ec 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -469,6 +469,55 @@ static int a5xx_ucode_init(struct msm_gpu *gpu) return 0; } +static int a5xx_zap_shader_resume(struct msm_gpu *gpu) +{ + int ret; + + ret = qcom_scm_gpu_zap_resume(); + if (ret) + DRM_ERROR("%s: zap-shader resume failed: %d\n", + gpu->name, ret); + + return ret; +} + +static int a5xx_zap_shader_init(struct msm_gpu *gpu) +{ + static bool loaded; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct platform_device *pdev = a5xx_gpu->pdev; + struct device_node *node; + int ret; + + /* + * If the zap shader is already loaded into memory we just need to kick + * the remote processor to reinitialize it + */ + if (loaded) + return a5xx_zap_shader_resume(gpu); + + /* Populate the sub-nodes if they haven't already been done */ + of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + + /* Find the sub-node for the zap shader */ + node = of_find_node_by_name(pdev->dev.of_node, "qcom,zap-shader"); + if (!node) { + DRM_ERROR("%s: qcom,zap-shader not found in device tree\n", + gpu->name); + return -ENODEV; + } + + ret = _pil_tz_load_image(of_find_device_by_node(node)); + if (ret) + DRM_ERROR("%s: Unable to load the zap shader\n", + gpu->name); + + loaded = !ret; + + return ret; +} + #define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \ @@ -653,8 +702,27 @@ static int a5xx_hw_init(struct msm_gpu *gpu) return -EINVAL; } - /* Put the GPU into unsecure mode */ - gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); + /* + * Try to load a zap shader into the secure world. If successful + * we can use the CP to switch out of secure mode. If not then we + * have no resource but to try to switch ourselves out manually. If we + * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will + * be blocked and a permissions violation will soon follow. + */ + ret = a5xx_zap_shader_init(gpu); + if (!ret) { + OUT_PKT7(gpu->rb, CP_SET_SECURE_MODE, 1); + OUT_RING(gpu->rb, 0x00000000); + + gpu->funcs->flush(gpu); + if (!gpu->funcs->idle(gpu)) + return -EINVAL; + } else { + /* Print a warning so if we die, we know why */ + dev_warn_once(gpu->dev->dev, + "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); + } return 0; }