From patchwork Thu Dec 15 12:21:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dwivedi, Avaneesh Kumar (avani)" X-Patchwork-Id: 9476021 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF1C160826 for ; Thu, 15 Dec 2016 12:29:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B898D28767 for ; Thu, 15 Dec 2016 12:29:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AC72A28764; Thu, 15 Dec 2016 12:29:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25FCD28765 for ; Thu, 15 Dec 2016 12:29:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936360AbcLOM3S (ORCPT ); Thu, 15 Dec 2016 07:29:18 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34954 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936216AbcLOM2w (ORCPT ); Thu, 15 Dec 2016 07:28:52 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C870461632; Thu, 15 Dec 2016 12:21:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1481804518; bh=HsqRmrNNl1GNAGXV9NpIXDzVTbUjCEn7uht03dSSdhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A1O+R4jHXZInqZFxJ+MaaJu4Eivlj0GJa2UuJE+v8Cnh0zh61JAPxex45hHODQwT+ iFzlLC+0OSDvB+Sj/vz4JURxS5gNq53Oi8VsLUpC18ULJA2ruy5uePGdo3hRz7+U3Q jrAcasYjdufEXSycwDxfy19/+DUratpaKK/xDr2o= Received: from akdwived-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akdwived@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 720B06161F; Thu, 15 Dec 2016 12:21:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1481804518; bh=HsqRmrNNl1GNAGXV9NpIXDzVTbUjCEn7uht03dSSdhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A1O+R4jHXZInqZFxJ+MaaJu4Eivlj0GJa2UuJE+v8Cnh0zh61JAPxex45hHODQwT+ iFzlLC+0OSDvB+Sj/vz4JURxS5gNq53Oi8VsLUpC18ULJA2ruy5uePGdo3hRz7+U3Q jrAcasYjdufEXSycwDxfy19/+DUratpaKK/xDr2o= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 720B06161F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=akdwived@codeaurora.org From: Avaneesh Kumar Dwivedi To: bjorn.andersson@linaro.org Cc: sboyd@codeaurora.org, agross@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, Avaneesh Kumar Dwivedi Subject: [PATCH v5 5/7] remoteproc: qcom: Modify clock enable and disable interface. Date: Thu, 15 Dec 2016 17:51:28 +0530 Message-Id: <1481804490-8583-6-git-send-email-akdwived@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481804490-8583-1-git-send-email-akdwived@codeaurora.org> References: <1481804490-8583-1-git-send-email-akdwived@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Clock enable/disable routine will get additional input parameter of pointer of array of clock struct's and clock count, it will use these pre initialized values to turn them up/down. Signed-off-by: Avaneesh Kumar Dwivedi --- drivers/remoteproc/qcom_q6v5_pil.c | 85 ++++++++++++++++++++++++++------------ 1 file changed, 58 insertions(+), 27 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c index e19fb9d..1018b8f 100644 --- a/drivers/remoteproc/qcom_q6v5_pil.c +++ b/drivers/remoteproc/qcom_q6v5_pil.c @@ -140,11 +140,6 @@ struct q6v5 { int active_reg_count; int proxy_reg_count; - - struct clk *ahb_clk; - struct clk *axi_clk; - struct clk *rom_clk; - struct completion start_done; struct completion stop_done; bool running; @@ -252,6 +247,38 @@ static void q6v5_regulator_disable(struct q6v5 *qproc, } } + +static int q6v5_clk_enable(struct device *dev, + struct clk **clks, int count) +{ + int rc; + int i; + + for (i = 0; i < count; i++) { + rc = clk_prepare_enable(clks[i]); + if (rc) { + dev_err(dev, "Clock enable failed\n"); + goto err; + } + } + + return 0; +err: + for (i--; i >= 0; i--) + clk_disable_unprepare(clks[i]); + + return rc; +} + +static void q6v5_clk_disable(struct device *dev, + struct clk **clks, int count) +{ + int i; + + for (i = 0; i < count; i++) + clk_disable_unprepare(clks[i]); +} + static int q6v5_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5 *qproc = rproc->priv; @@ -548,11 +575,18 @@ static int q6v5_start(struct rproc *rproc) return ret; } + ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, + qproc->proxy_clk_count); + if (ret) { + dev_err(qproc->dev, "failed to enable proxy clocks\n"); + goto disable_proxy_reg; + } + ret = q6v5_regulator_enable(qproc, qproc->active_regs, qproc->active_reg_count); if (ret) { dev_err(qproc->dev, "failed to enable supplies\n"); - goto disable_proxy_reg; + goto disable_proxy_clk; } ret = reset_control_deassert(qproc->mss_restart); if (ret) { @@ -560,17 +594,12 @@ static int q6v5_start(struct rproc *rproc) goto disable_vdd; } - ret = clk_prepare_enable(qproc->ahb_clk); - if (ret) + ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, + qproc->active_clk_count); + if (ret) { + dev_err(qproc->dev, "failed to enable clocks\n"); goto assert_reset; - - ret = clk_prepare_enable(qproc->axi_clk); - if (ret) - goto disable_ahb_clk; - - ret = clk_prepare_enable(qproc->rom_clk); - if (ret) - goto disable_axi_clk; + } writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); @@ -605,25 +634,26 @@ static int q6v5_start(struct rproc *rproc) qproc->running = true; - /* TODO: All done, release the handover resources */ - + q6v5_clk_disable(qproc->dev, qproc->proxy_clks, + qproc->proxy_clk_count); + q6v5_regulator_disable(qproc, qproc->proxy_regs, + qproc->proxy_reg_count); return 0; halt_axi_ports: q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); - - clk_disable_unprepare(qproc->rom_clk); -disable_axi_clk: - clk_disable_unprepare(qproc->axi_clk); -disable_ahb_clk: - clk_disable_unprepare(qproc->ahb_clk); + q6v5_clk_disable(qproc->dev, qproc->active_clks, + qproc->active_clk_count); assert_reset: reset_control_assert(qproc->mss_restart); disable_vdd: q6v5_regulator_disable(qproc, qproc->active_regs, qproc->active_reg_count); +disable_proxy_clk: + q6v5_clk_disable(qproc->dev, qproc->proxy_clks, + qproc->proxy_clk_count); disable_proxy_reg: q6v5_regulator_disable(qproc, qproc->proxy_regs, qproc->proxy_reg_count); @@ -652,9 +682,10 @@ static int q6v5_stop(struct rproc *rproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); reset_control_assert(qproc->mss_restart); - clk_disable_unprepare(qproc->rom_clk); - clk_disable_unprepare(qproc->axi_clk); - clk_disable_unprepare(qproc->ahb_clk); + q6v5_clk_disable(qproc->dev, qproc->active_clks, + qproc->active_clk_count); + q6v5_clk_disable(qproc->dev, qproc->proxy_clks, + qproc->proxy_clk_count); q6v5_regulator_disable(qproc, qproc->active_regs, qproc->active_reg_count); q6v5_regulator_disable(qproc, qproc->proxy_regs,