From patchwork Sat Jan 7 13:10:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9503035 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D71D5606E1 for ; Sat, 7 Jan 2017 13:11:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8680284B0 for ; Sat, 7 Jan 2017 13:11:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD0F3284C0; Sat, 7 Jan 2017 13:11:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D1D3284B0 for ; Sat, 7 Jan 2017 13:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937696AbdAGNLK (ORCPT ); Sat, 7 Jan 2017 08:11:10 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:60374 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932228AbdAGNLJ (ORCPT ); Sat, 7 Jan 2017 08:11:09 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A24C061283; Sat, 7 Jan 2017 13:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483794661; bh=PInFfitW3ILL9dXxJPD+CiIqSwGJGKAZZqBimoHk+g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NTzhzGe2Gip16Immk83QA0rnzdq27EJ973WKIJePT0CKFXDGVEAqRend2UMTbe7jr yGT3lZvbVtxFyXLkFo5mQUDLU4benoz/D+yBfuibqCa8dIVu4oX6sgw65Hyb7ub5uR 5Fw32WoGhGQxKdFXNd3FWdQpl9cgVoJ4OPD8FTus= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 242126126C; Sat, 7 Jan 2017 13:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483794660; bh=PInFfitW3ILL9dXxJPD+CiIqSwGJGKAZZqBimoHk+g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ccblvIj4lTGSK3i6TRjIFXeC+gQAaDUjMKk2cGaHvg7o7lzOgjTTZINGVyaJ4a2MW UikcByyuwGYF56dguZRTG5bDB0ForTF1SNw6ucaYNf0LII5rRmJtwCOXqJOPCM5tLX qlV7dGtmPo47DZis5LAvEzB+WKPSWostDbvbu1Ps= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 242126126C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Archit Taneja Subject: [PATCH 03/10] drm/msm/dsi: Add a PHY op that initializes version specific stuff Date: Sat, 7 Jan 2017 18:40:35 +0530 Message-Id: <1483794642-2184-4-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483794642-2184-1-git-send-email-architt@codeaurora.org> References: <1483794642-2184-1-git-send-email-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Create an init() op for dsi_phy which sets up things specific to a given DSI PHY. The dsi_phy driver probe expects every DSI version to get a "dsi_phy_regulator" mmio base. This isn't the case for 8x96. Creating an init() op will allow us to accommodate such differences. Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 33 ++++++++++++++++++------- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 1 + 5 files changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index f39386e..03a3549 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy) return -EINVAL; } +int msm_dsi_phy_init_common(struct msm_dsi_phy *phy) +{ + struct platform_device *pdev = phy->pdev; + int ret = 0; + + phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", + "DSI_PHY_REG"); + if (IS_ERR(phy->reg_base)) { + dev_err(&pdev->dev, "%s: failed to map phy regulator base\n", + __func__); + ret = -ENOMEM; + goto fail; + } + +fail: + return ret; +} + static int dsi_phy_driver_probe(struct platform_device *pdev) { struct msm_dsi_phy *phy; @@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } - phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", - "DSI_PHY_REG"); - if (IS_ERR(phy->reg_base)) { - dev_err(dev, "%s: failed to map phy regulator base\n", - __func__); - ret = -ENOMEM; - goto fail; - } - ret = dsi_phy_regulator_init(phy); if (ret) { dev_err(dev, "%s: failed to init regulator\n", __func__); @@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + if (phy->cfg->ops.init) { + ret = phy->cfg->ops.init(phy); + if (ret) + goto fail; + } + /* PLL init will call into clk_register which requires * register access, so we need to enable power and ahb clock. */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index f24a854..b9d7d02 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -22,6 +22,7 @@ #define dsi_phy_write(offset, data) msm_writel((data), (offset)) struct msm_dsi_phy_ops { + int (*init) (struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, const unsigned long bit_rate, const unsigned long esc_rate); void (*disable)(struct msm_dsi_phy *phy); @@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, const unsigned long bit_rate, const unsigned long esc_rate); void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, u32 bit_mask); +int msm_dsi_phy_init_common(struct msm_dsi_phy *phy); #endif /* __DSI_PHY_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index c757e20..c4a7be5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -145,6 +145,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) .ops = { .enable = dsi_20nm_phy_enable, .disable = dsi_20nm_phy_disable, + .init = msm_dsi_phy_init_common, }, .io_start = { 0xfd998300, 0xfd9a0300 }, .num_dsi_phy = 2, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 63d7fba..ea740c5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -144,6 +144,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .init = msm_dsi_phy_init_common, }, .io_start = { 0xfd922b00, 0xfd923100 }, .num_dsi_phy = 2, @@ -161,6 +162,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .init = msm_dsi_phy_init_common, }, .io_start = { 0x1a98500 }, .num_dsi_phy = 1, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 7bdb9de..9aff0ba 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -191,6 +191,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, + .init = msm_dsi_phy_init_common, }, .io_start = { 0x4700300, 0x5800300 }, .num_dsi_phy = 2,