From patchwork Sat Jan 7 13:10:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9503049 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF69F60710 for ; Sat, 7 Jan 2017 13:11:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0EC2284B0 for ; Sat, 7 Jan 2017 13:11:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B5D9C284B4; Sat, 7 Jan 2017 13:11:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DA6D284B3 for ; Sat, 7 Jan 2017 13:11:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937818AbdAGNLY (ORCPT ); Sat, 7 Jan 2017 08:11:24 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:60604 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937720AbdAGNLW (ORCPT ); Sat, 7 Jan 2017 08:11:22 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D57EB6120F; Sat, 7 Jan 2017 13:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483794674; bh=WqPvup26Yh7/V7mCfg2jIv3iQ42YKMdXllglkh2Zd2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o3BpTvipYfOtHjtPrlO8tFDCYeRx/ogDlZTZWe7yb0fGU9pkLDX7P7NuE0eDTYoG9 7SxmhGjVUmAMvdmd9UVOEN8O/phArrRYI7rl9Pnys2tjDAxgNpEkS1CA4Mb/xMDowU VGQ3TgQAfc97CyyDuBXHp5Lp4y+gzx5mFsB4lFII= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4DAB36120F; Sat, 7 Jan 2017 13:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483794674; bh=WqPvup26Yh7/V7mCfg2jIv3iQ42YKMdXllglkh2Zd2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o3BpTvipYfOtHjtPrlO8tFDCYeRx/ogDlZTZWe7yb0fGU9pkLDX7P7NuE0eDTYoG9 7SxmhGjVUmAMvdmd9UVOEN8O/phArrRYI7rl9Pnys2tjDAxgNpEkS1CA4Mb/xMDowU VGQ3TgQAfc97CyyDuBXHp5Lp4y+gzx5mFsB4lFII= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 4DAB36120F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Archit Taneja Subject: [PATCH 06/10] drm/msm/dsi: Reset both PHYs before clock operation for dual DSI Date: Sat, 7 Jan 2017 18:40:38 +0530 Message-Id: <1483794642-2184-7-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483794642-2184-1-git-send-email-architt@codeaurora.org> References: <1483794642-2184-1-git-send-email-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In case of dual DSI, some registers in PHY1 have been programmed during PLL0 clock's set_rate. The PHY1 reset called by host1 later will silently reset those PHY1 registers. This change is to reset and enable both PHYs before any PLL clock operation. [Originally worked on by Hai Li . Fixed up by Archit Taneja ] Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/dsi/dsi.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 25 +++++++++++++------------ drivers/gpu/drm/msm/dsi/dsi_manager.c | 32 +++++++++++++++++++++++++++++--- 3 files changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index d516fe2..9407a68 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -166,6 +166,7 @@ struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, void msm_dsi_host_unregister(struct mipi_dsi_host *host); int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, struct msm_dsi_pll *src_pll); +void msm_dsi_host_reset_phy(struct mipi_dsi_host *host); void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 6709701..b7fd952 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -691,17 +691,6 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) return 0; } -static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host) -{ - DBG(""); - dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); - /* Make sure fully reset */ - wmb(); - udelay(1000); - dsi_write(msm_host, REG_DSI_PHY_RESET, 0); - udelay(100); -} - static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) { u32 intr; @@ -2126,6 +2115,19 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, return ret; } +void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + DBG(""); + dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); + /* Make sure fully reset */ + wmb(); + udelay(1000); + dsi_write(msm_host, REG_DSI_PHY_RESET, 0); + udelay(100); +} + int msm_dsi_host_enable(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); @@ -2206,7 +2208,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host) goto fail_disable_reg; } - dsi_phy_sw_reset(msm_host); ret = msm_dsi_manager_phy_enable(msm_host->id, msm_host->byte_clk_rate * 8, msm_host->esc_clk_rate, diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index fbd11dc..0c7a631 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -660,13 +660,39 @@ int msm_dsi_manager_phy_enable(int id, struct msm_dsi_phy_shared_timings *shared_timings) { struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER); + struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); struct msm_dsi_phy *phy = msm_dsi->phy; int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id; int ret; - ret = msm_dsi_phy_enable(phy, src_pll_id, bit_rate, esc_rate); - if (ret) - return ret; + /* In case of dual DSI, some registers in PHY1 have been programmed + * during PLL0 clock's set_rate. The PHY1 reset called by host1 here + * will silently reset those PHY1 registers. Therefore we need to reset + * and enable both PHYs before any PLL clock operation. + */ + if (IS_DUAL_DSI() && mdsi && sdsi) { + if (!mdsi->phy_enabled && !sdsi->phy_enabled) { + msm_dsi_host_reset_phy(mdsi->host); + msm_dsi_host_reset_phy(sdsi->host); + ret = msm_dsi_phy_enable(mdsi->phy, src_pll_id, + bit_rate, esc_rate); + if (ret) + return ret; + ret = msm_dsi_phy_enable(sdsi->phy, src_pll_id, + bit_rate, esc_rate); + if (ret) { + msm_dsi_phy_disable(mdsi->phy); + return ret; + } + } + } else { + msm_dsi_host_reset_phy(msm_dsi->host); + ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, bit_rate, + esc_rate); + if (ret) + return ret; + } msm_dsi->phy_enabled = true; msm_dsi_phy_get_shared_timings(phy, shared_timings);