From patchwork Thu Mar 9 15:35:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 9613567 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 16255604D9 for ; Thu, 9 Mar 2017 15:36:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA6C128676 for ; Thu, 9 Mar 2017 15:36:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF0962867A; Thu, 9 Mar 2017 15:36:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68F2728676 for ; Thu, 9 Mar 2017 15:36:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754953AbdCIPge (ORCPT ); Thu, 9 Mar 2017 10:36:34 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56700 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754933AbdCIPga (ORCPT ); Thu, 9 Mar 2017 10:36:30 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6472E607A0; Thu, 9 Mar 2017 15:36:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1489073784; bh=nO1m5rWVx0yI3beyrFfjKDzmyeOAqmwCLEZ3ij16rm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nDmlgEr7GjDWoKU3wUJhH7ft4M68JOKwLxF7LsXutBS2mjVg9WBeogYAxifp9CMZz zrwFpa+PgkSgycgQjqlLEDB8Vo79q/jlqCDQgS6pWZ0c3zAW4ECBhyjncsz+6ikvNy A/ljCwAwsajErcdlg33wqZP7+iZSolc6g/pKd8zs= Received: from blr-ubuntu-32.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B2DED607CD; Thu, 9 Mar 2017 15:36:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1489073783; bh=nO1m5rWVx0yI3beyrFfjKDzmyeOAqmwCLEZ3ij16rm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i6jqAzfYKWRJpS7tOAx9lWzrME0ENWdrc8xHBtlUkEl8BPf+ValW8+qFYthZF1Aud 7y/JKG0p6453/94P2pt7ur9P3HpckiaofGjaqoEeSd5XSu6VPDS7gfVJbZ3CUm/Ey6 3sMtSpiFLSDTWsC68EgAr2Y2ZN1KgkozhGHVdNoM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B2DED607CD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: robin.murphy@arm.com, will.deacon@arm.com, joro@8bytes.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, m.szyprowski@samsung.com, linux-clk@vger.kernel.org, sboyd@codeaurora.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mathieu.poirier@linaro.org, mark.rutland@arm.com Cc: sricharan@codeaurora.org Subject: [PATCH V3 2/5] iommu/arm-smmu: Add support for MMU40x/500 clocks Date: Thu, 9 Mar 2017 21:05:45 +0530 Message-Id: <1489073748-3659-3-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1489073748-3659-1-git-send-email-sricharan@codeaurora.org> References: <1489073748-3659-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming interface as well, clocked using the TCU_CLK. The TBU can also be sharing the same clock domain as TCU, in which case both are clocked using the TCU_CLK. This defines the clock bindings for the same and adds the init, enable and disable functions for handling the clocks. Signed-off-by: Sricharan R --- .../devicetree/bindings/iommu/arm,smmu.txt | 27 ++++++ drivers/iommu/arm-smmu.c | 95 +++++++++++++++++++++- 2 files changed, 121 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 6cdf32d..b369c13 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -60,6 +60,28 @@ conditions. aliases of secure registers have to be used during SMMU configuration. +- clock-names: Should be "tbu_clk" and "tcu_clk" and "cfg_clk" for + "arm,mmu-400", "arm,mmu-401" and "arm,mmu-500" + + "tcu_clk" is required for smmu's register access using the + programming interface and ptw for downstream bus access. + + "tbu_clk" is required for access to the TBU connected to the + master locally. This clock is optional and not required when + TBU is in the same clock domain as the TCU or when the TBU is + clocked along with the master. + + "cfg_clk" is optional if required to access the TCU's programming + interface, apart from the "tcu_clk". + +- clocks: Phandles for respective clocks described by clock-names. + +- power-domains: Phandles to SMMU's power domain specifier. This is + required even if SMMU belongs to the master's power + domain, as the SMMU will have to be enabled and + accessed before master gets enabled and linked to its + SMMU. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -84,6 +106,11 @@ conditions. <0 36 4>, <0 37 4>; #iommu-cells = <1>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>, + <&gcc GCC_MDP_TBU_CLK>; + + clock-names = "cfg_clk", "tcu_clk", "tbu_clk"; }; /* device with two stream IDs, 0 and 7 */ diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index f7e11d3..720a1ef 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -341,6 +341,12 @@ struct arm_smmu_master_cfg { #define for_each_cfg_sme(fw, i, idx) \ for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i) +struct mmu500_clk { + struct clk *cfg_clk; + struct clk *tcu_clk; + struct clk *tbu_clk; +}; + struct arm_smmu_clks { void *clks; int (*init_clocks)(struct arm_smmu_device *smmu); @@ -455,6 +461,92 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) return container_of(dom, struct arm_smmu_domain, domain); } +static int mmu500_enable_clocks(struct arm_smmu_device *smmu) +{ + int ret = 0; + struct mmu500_clk *sclks = smmu->smmu_clks.clks; + + if (!sclks) + return 0; + + ret = clk_prepare_enable(sclks->cfg_clk); + if (ret) { + dev_err(smmu->dev, "Couldn't enable cfg_clk"); + return ret; + } + + ret = clk_prepare_enable(sclks->tcu_clk); + if (ret) { + dev_err(smmu->dev, "Couldn't enable tcu_clk"); + clk_disable_unprepare(sclks->cfg_clk); + return ret; + } + + ret = clk_prepare_enable(sclks->tbu_clk); + if (ret) { + dev_err(smmu->dev, "Couln't enable tbu_clk"); + clk_disable_unprepare(sclks->tcu_clk); + clk_disable_unprepare(sclks->cfg_clk); + return ret; + } + + return 0; +} + +static void mmu500_disable_clocks(struct arm_smmu_device *smmu) +{ + struct mmu500_clk *sclks = smmu->smmu_clks.clks; + + if (!sclks) { + clk_disable_unprepare(sclks->tbu_clk); + clk_disable_unprepare(sclks->tcu_clk); + clk_disable_unprepare(sclks->cfg_clk); + } +} + +static int mmu500_init_clocks(struct arm_smmu_device *smmu) +{ + struct device *dev = smmu->dev; + struct mmu500_clk *sclks; + int err; + + if (!of_find_property(dev->of_node, "clocks", NULL)) + return 0; + + sclks = devm_kzalloc(dev, sizeof(*sclks), GFP_KERNEL); + if (!sclks) + return -ENOMEM; + + sclks->cfg_clk = devm_clk_get(dev, "cfg_clk"); + if (IS_ERR(sclks->cfg_clk)) { + err = PTR_ERR(sclks->cfg_clk); + /* Ignore all, except -EPROBE_DEFER for optional clocks */ + if (err == -EPROBE_DEFER) + return err; + else + sclks->cfg_clk = NULL; + } + + sclks->tcu_clk = devm_clk_get(dev, "tcu_clk"); + if (IS_ERR(sclks->tcu_clk)) { + dev_err(dev, "Couldn't get tcu_clk"); + return PTR_ERR(sclks->tcu_clk); + } + + sclks->tbu_clk = devm_clk_get(dev, "tbu_clk"); + if (IS_ERR(sclks->tbu_clk)) { + err = PTR_ERR(sclks->tbu_clk); + /* Ignore all, ecept -EPROBE_DEFER for optional clocks */ + if (err == -EPROBE_DEFER) + return err; + else + sclks->tbu_clk = NULL; + } + + smmu->smmu_clks.clks = sclks; + return 0; +} + static void parse_driver_options(struct arm_smmu_device *smmu) { int i = 0; @@ -1981,7 +2073,8 @@ struct arm_smmu_match_data { NULL, NULL, NULL); ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU, NULL, NULL, NULL); -ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, NULL, NULL, NULL); +ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, mmu500_init_clocks, + mmu500_enable_clocks, mmu500_disable_clocks); ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2, NULL, NULL, NULL);