From patchwork Tue May 30 12:39:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Gunda X-Patchwork-Id: 9754541 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 89D8460390 for ; Tue, 30 May 2017 12:41:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C8262847A for ; Tue, 30 May 2017 12:41:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 715A42847E; Tue, 30 May 2017 12:41:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 169142848B for ; Tue, 30 May 2017 12:41:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751554AbdE3MlG (ORCPT ); Tue, 30 May 2017 08:41:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58332 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751412AbdE3MlE (ORCPT ); Tue, 30 May 2017 08:41:04 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1710460912; Tue, 30 May 2017 12:40:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1496148049; bh=CHt0Z52mKwrfXySJv42vqY1I3Kr/X+0oW9OdxHgB3YA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cDVdSGs4zZqMWlxi4U8Tju6kgihWbH52TEr4aWckEZD8Rp7Wdh0YcZWpakdprETyI fpGVU9n0VE07qP+Pkxkvwtbw5MDAtKFiwiEnZ5MfDPEYGXTV9GmKhsRRuxGe1atuP7 hIaWysytJz9AeCKEI7v6UwyZ9ZnRwrUU/QJdYk5o= Received: from kgunda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kgunda@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 80D92608CF; Tue, 30 May 2017 12:40:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1496148048; bh=CHt0Z52mKwrfXySJv42vqY1I3Kr/X+0oW9OdxHgB3YA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H9qkuVCW0OpCsN6m4dyWv1kcUOHUwJeUhPJOXmqLgtw7M1xS/O7re0jIptAPy1TkA /QLmBp7LQf+tuQxqgXIPkghmSb8DHE0swV9yjp0WY6ROZF2FEHp7YQH3AJLnYRAbxy SEEJzE3sUuR6D8pQ2GRjmRZ3AlsSuYKw1W70UpYY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 80D92608CF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=kgunda@codeaurora.org From: Kiran Gunda To: Kiran Gunda , Abhijeet Dharmapurikar , David Collins , Christophe JAILLET , Subbaraman Narayanamurthy , linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, adharmap@quicinc.com, aghayal@qti.qualcomm.com, sboyd@codeaurora.org Subject: [PATCH V1 14/15] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Tue, 30 May 2017 18:09:02 +0530 Message-Id: <1496147943-25822-15-git-send-email-kgunda@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496147943-25822-1-git-send-email-kgunda@codeaurora.org> References: <1496147943-25822-1-git-send-email-kgunda@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Kiran Gunda --- drivers/spmi/spmi-pmic-arb.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index b755c24..767bd2c 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -522,24 +522,9 @@ static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) static void cleanup_irq(struct spmi_pmic_arb *pa, u16 apid, int id) { - u16 ppid = pa->apid_data[apid].ppid; - u8 sid = ppid >> 8; - u8 per = ppid & 0xFF; u8 irq_mask = BIT(id); writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid)); - - if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pa->spmic->dev, - "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pa->spmic->dev, - "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid) @@ -698,6 +683,17 @@ static int qpnpint_get_irqchip_state(struct irq_data *d, | IRQCHIP_SKIP_SET_WAKE, }; +static void qpnpint_irq_domain_activate(struct irq_domain *domain, + struct irq_data *d) +{ + u8 irq = HWIRQ_IRQ(d->hwirq); + u8 buf; + + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); +} + static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, struct device_node *controller, const u32 *intspec, @@ -1164,6 +1160,7 @@ static u32 pmic_arb_channel_map_offset_v5(u16 n) static const struct irq_domain_ops pmic_arb_irq_domain_ops = { .map = qpnpint_irq_domain_map, .xlate = qpnpint_irq_domain_dt_translate, + .activate = qpnpint_irq_domain_activate, }; static int spmi_pmic_arb_probe(struct platform_device *pdev)