From patchwork Tue May 30 12:38:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Gunda X-Patchwork-Id: 9754555 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D82C9602B9 for ; Tue, 30 May 2017 12:42:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA2B92846A for ; Tue, 30 May 2017 12:42:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BE9332847A; Tue, 30 May 2017 12:42:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 514392846A for ; Tue, 30 May 2017 12:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751603AbdE3Mme (ORCPT ); Tue, 30 May 2017 08:42:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57322 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751556AbdE3MkO (ORCPT ); Tue, 30 May 2017 08:40:14 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1769F607E4; Tue, 30 May 2017 12:40:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1496148014; bh=KUMyEMUN1CS49Ga/SoiVWOePPgRdNiNjXUNi28n+XtI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZsFSd5J3xw0YSCavM27Jpd3MawVuzUxWSkMfsT+LFRGMbj05KlDHejN5vcDVNKQXS 6/K6pcMs4DmxT0QK1TpjevT0bvkv49ys7co769g6hFwEK8WKoTdN/wlOjAXPw7FKLv YY8OMPouFQx/qOSSNF4jekuSzUOz2PzEkEBUsyjo= Received: from kgunda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kgunda@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CACA6607C8; Tue, 30 May 2017 12:40:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1496148013; bh=KUMyEMUN1CS49Ga/SoiVWOePPgRdNiNjXUNi28n+XtI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZP9u676J9tVjZhmKwaz2wQi+8Qy2Ud8Pa3fnA6kt6CSFXOXF6GjFCxFK7abppgi5z BPQE62VAbJF7IGFI96jAtlZeymuV9tC7NLsI02kKxhgOO5dtrIbOUptaFQpLc6AXZf ER/mjhDEh7x/fWjsgXkaHGGW9pWGMSp7OR2jOTtY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CACA6607C8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=kgunda@codeaurora.org From: Kiran Gunda To: Kiran Gunda , Abhijeet Dharmapurikar , Christophe JAILLET , Subbaraman Narayanamurthy , David Collins , linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, adharmap@quicinc.com, aghayal@qti.qualcomm.com, sboyd@codeaurora.org Subject: [PATCH V1 07/15] spmi: pmic-arb: clear the latched status of the interrupt Date: Tue, 30 May 2017 18:08:55 +0530 Message-Id: <1496147943-25822-8-git-send-email-kgunda@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496147943-25822-1-git-send-email-kgunda@codeaurora.org> References: <1496147943-25822-1-git-send-email-kgunda@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Abhijeet Dharmapurikar PMIC interrupts each have an internal latched status bit which is not visible from any register. This status bit is set as soon as the conditions specified in the interrupt type and polarity registers are met even if the interrupt is not enabled. When it is set, nothing else changes within the PMIC and no interrupt notification packets are sent. If the internal latched status bit is set when an interrupt is enabled, then the value is immediately propagated into the interrupt latched status register and an interrupt notification packet is sent out from the PMIC over SPMI. This PMIC hardware behavior can lead to a situation where the handler for a level triggered interrupt is called immediately after enable_irq() is called even though the interrupt physically triggered while it was disabled within the genirq framework. This situation takes place if the the interrupt fires twice after calling disable_irq(). The first time it fires, the level flow handler will mask and disregard it. Unfortunately, the second time it fires, the internal latched status bit is set within the PMIC and no further notification is received. When enable_irq() is called later, the interrupt is unmasked (enabled in the PMIC) which results in the PMIC immediately sending an interrupt notification packet out over SPMI. This breaks the semantics of level triggered interrupts within the genirq framework since they should be completely ignored while disabled. The PMIC internal latched status behavior also affects how interrupts are treated during suspend. While entering suspend, all interrupts not specified as wakeup mode are masked. Upon resume, these interrupts are unmasked. Thus if any of the non-wakeup PMIC interrupts fired while the system was suspended, then the PMIC will send interrupt notification packets out via SPMI as soon as they are unmasked during resume. This behavior violates genirq semantics as well since non-wakeup interrupts should be completely ignored during suspend. Modify the qpnpint_irq_unmask() function so that the interrupt latched status clear register is written immediately before the interrupt enable register. This clears the internal latched status bit of the interrupt so that it cannot trigger spuriously immediately upon being enabled. Also, while resuming an irq, an unmask could be called even if it was not previously masked. So, before writing these registers, check if the interrupt is already enabled within the PMIC. If it is, then no further register writes are required. This condition check ensures that a valid latched status register bit is not cleared until it is properly handled. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: Kiran Gunda Reviewed-by: Stephen Boyd --- drivers/spmi/spmi-pmic-arb.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index bc03737..1d23df0 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -580,12 +580,22 @@ static void qpnpint_irq_unmask(struct irq_data *d) struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); u8 irq = d->hwirq >> 8; u8 apid = d->hwirq; - u8 data = BIT(irq); + u8 buf[2]; writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, pa->intr + pa->ver_ops->acc_enable(apid)); - qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); + qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); + if (!(buf[0] & BIT(irq))) { + /* + * Since the interrupt is currently disabled, write to both the + * LATCHED_CLR and EN_SET registers so that a spurious interrupt + * cannot be triggered when the interrupt is enabled + */ + buf[0] = BIT(irq); + buf[1] = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); + } } static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)