From patchwork Thu Jul 13 21:52:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 9839607 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B40DA60392 for ; Thu, 13 Jul 2017 21:52:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1B6128794 for ; Thu, 13 Jul 2017 21:52:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D696228797; Thu, 13 Jul 2017 21:52:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3DC6028794 for ; Thu, 13 Jul 2017 21:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752898AbdGMVww (ORCPT ); Thu, 13 Jul 2017 17:52:52 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55668 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752774AbdGMVwu (ORCPT ); Thu, 13 Jul 2017 17:52:50 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E50EF612E2; Thu, 13 Jul 2017 21:52:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1499982769; bh=7wNxrJOkW3bV5aL3VCmNsC6vVgkqfG2iCGAGjOO9Pzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cUoVkkHyV6OjUI5dtMyKe7Xod6dFVcMyMXKAHhmMWcj46Sbb3lknLHHqeJjh26yni iEyp6D0qFpzbDDNCFLUUGBuzkGb5yLOB8ws4HPXbNAEAwR3DS15O28I46CX+dkojJ/ yvhkLcq9+DPfcyiJdq3ogHVwoPjftsPe65pKknFU= Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4EDF0612CA; Thu, 13 Jul 2017 21:52:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1499982769; bh=7wNxrJOkW3bV5aL3VCmNsC6vVgkqfG2iCGAGjOO9Pzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cUoVkkHyV6OjUI5dtMyKe7Xod6dFVcMyMXKAHhmMWcj46Sbb3lknLHHqeJjh26yni iEyp6D0qFpzbDDNCFLUUGBuzkGb5yLOB8ws4HPXbNAEAwR3DS15O28I46CX+dkojJ/ yvhkLcq9+DPfcyiJdq3ogHVwoPjftsPe65pKknFU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4EDF0612CA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: andy.gross@linaro.org, david.brown@linaro.org, Linus Walleij , Bjorn Andersson , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: timur@codeaurora.org Subject: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 Date: Thu, 13 Jul 2017 16:52:43 -0500 Message-Id: <1499982763-29619-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499982763-29619-1-git-send-email-timur@codeaurora.org> References: <1499982763-29619-1-git-send-email-timur@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Newer versions of the firmware for the Qualcomm Datacenter Technologies QDF2400 restricts access to a subset of the GPIOs on the TLMM. To prevent older kernels from accidentally accessing the restricted GPIOs, we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002, and introduce a new property "gpios". This property is an array of specific GPIOs that are accessible. When an older kernel boots on newer (restricted) firmware, it will fail to probe. To implement the sparse GPIO map, we register all of the GPIOs, but set the pin count for the unavailable GPIOs to zero. The pinctrl-msm driver will block those unavailable GPIOs from being accessed. To allow newer kernels to support older firmware, the driver retains support for QCOM8001. Signed-off-by: Timur Tabi --- drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++---------- 1 file changed, 111 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index bb3ce5c..266f2e6 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -38,83 +38,148 @@ /* maximum size of each gpio name (enough room for "gpioXXX" + null) */ #define NAME_SIZE 8 +enum { + QDF2XXX_V1, + QDF2XXX_V2, +}; + +static const struct acpi_device_id qdf2xxx_acpi_ids[] = { + {"QCOM8001", QDF2XXX_V1}, + {"QCOM8002", QDF2XXX_V2}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); + static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) { + const struct acpi_device_id *id = + acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev); + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct msm_pingroup *groups; char (*names)[NAME_SIZE]; unsigned int i; - u32 num_gpios; + unsigned int num_gpios; /* The number of GPIOs we support */ + u32 max_gpios; /* The highest number GPIO that exists */ + u16 *gpios; /* An array of supported GPIOs */ int ret; - /* Query the number of GPIOs from ACPI */ - ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); + /* The total number of GPIOs that exist */ + ret = device_property_read_u32(dev, "num-gpios", &max_gpios); if (ret < 0) { - dev_warn(&pdev->dev, "missing num-gpios property\n"); + dev_err(dev, "missing or invalid 'num-gpios' property\n"); return ret; } + if (!max_gpios || max_gpios > MAX_GPIOS) { + dev_err(dev, "invalid 'num-gpios' property\n"); + return -EINVAL; + } - if (!num_gpios || num_gpios > MAX_GPIOS) { - dev_warn(&pdev->dev, "invalid num-gpios property\n"); - return -ENODEV; + /* + * The QCOM8001 HID contains only the number of GPIOs, and assumes + * that all of them are available. num_gpios is the same as max_gpios. + * + * The QCOM8002 HID introduces the 'gpios' DSD, which lists + * specific GPIOs that the driver is allowed to access. + * + * The make the common code simpler, in both cases we create an + * array of GPIOs that are accessible. So for QCOM8001, that would + * be all of the GPIOs. + */ + if (id->driver_data == QDF2XXX_V1) { + num_gpios = max_gpios; + + gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + for (i = 0; i < num_gpios; i++) + gpios[i] = i; + } else { + /* The number of GPIOs in the approved list */ + ret = device_property_read_u16_array(dev, "gpios", NULL, 0); + if (ret < 0) { + dev_err(dev, "missing/invalid 'gpios' property\n"); + return ret; + } + if (ret == 0) { + dev_warn(dev, "no GPIOs defined\n"); + return -ENODEV; + } + num_gpios = ret; + + gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + ret = device_property_read_u16_array(dev, "gpios", gpios, + num_gpios); + if (ret < 0) { + dev_err(dev, "could not read list of GPIOs\n"); + return ret; + } } - pins = devm_kcalloc(&pdev->dev, num_gpios, + pins = devm_kcalloc(dev, max_gpios, sizeof(struct pinctrl_pin_desc), GFP_KERNEL); - groups = devm_kcalloc(&pdev->dev, num_gpios, + groups = devm_kcalloc(dev, max_gpios, sizeof(struct msm_pingroup), GFP_KERNEL); - names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL); + names = devm_kcalloc(dev, num_gpios, NAME_SIZE, GFP_KERNEL); if (!pins || !groups || !names) return -ENOMEM; - for (i = 0; i < num_gpios; i++) { - snprintf(names[i], NAME_SIZE, "gpio%u", i); - + /* + * Initialize the array. GPIOs not listed in the 'gpios' array + * still need a number and a name, but nothing else. + */ + for (i = 0; i < max_gpios; i++) { pins[i].number = i; - pins[i].name = names[i]; - - groups[i].npins = 1; - groups[i].name = names[i]; groups[i].pins = &pins[i].number; + } - groups[i].ctl_reg = 0x10000 * i; - groups[i].io_reg = 0x04 + 0x10000 * i; - groups[i].intr_cfg_reg = 0x08 + 0x10000 * i; - groups[i].intr_status_reg = 0x0c + 0x10000 * i; - groups[i].intr_target_reg = 0x08 + 0x10000 * i; - - groups[i].mux_bit = 2; - groups[i].pull_bit = 0; - groups[i].drv_bit = 6; - groups[i].oe_bit = 9; - groups[i].in_bit = 0; - groups[i].out_bit = 1; - groups[i].intr_enable_bit = 0; - groups[i].intr_status_bit = 0; - groups[i].intr_target_bit = 5; - groups[i].intr_target_kpss_val = 1; - groups[i].intr_raw_status_bit = 4; - groups[i].intr_polarity_bit = 1; - groups[i].intr_detection_bit = 2; - groups[i].intr_detection_width = 2; + /* Populate the entries that are meant to be exposes as GPIOs. */ + for (i = 0; i < num_gpios; i++) { + unsigned int gpio = gpios[i]; + + groups[gpio].npins = 1; + snprintf(names[i], NAME_SIZE, "gpio%u", gpio); + pins[gpio].name = names[i]; + groups[gpio].name = names[i]; + + groups[gpio].ctl_reg = 0x10000 * gpio; + groups[gpio].io_reg = 0x04 + 0x10000 * gpio; + groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; + groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; + groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; + + groups[gpio].mux_bit = 2; + groups[gpio].pull_bit = 0; + groups[gpio].drv_bit = 6; + groups[gpio].oe_bit = 9; + groups[gpio].in_bit = 0; + groups[gpio].out_bit = 1; + groups[gpio].intr_enable_bit = 0; + groups[gpio].intr_status_bit = 0; + groups[gpio].intr_target_bit = 5; + groups[gpio].intr_target_kpss_val = 1; + groups[gpio].intr_raw_status_bit = 4; + groups[gpio].intr_polarity_bit = 1; + groups[gpio].intr_detection_bit = 2; + groups[gpio].intr_detection_width = 2; } + devm_kfree(dev, gpios); + qdf2xxx_pinctrl.pins = pins; qdf2xxx_pinctrl.groups = groups; - qdf2xxx_pinctrl.npins = num_gpios; - qdf2xxx_pinctrl.ngroups = num_gpios; - qdf2xxx_pinctrl.ngpios = num_gpios; + qdf2xxx_pinctrl.npins = max_gpios; + qdf2xxx_pinctrl.ngroups = max_gpios; + qdf2xxx_pinctrl.ngpios = max_gpios; return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl); } -static const struct acpi_device_id qdf2xxx_acpi_ids[] = { - {"QCOM8001"}, - {}, -}; -MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); - static struct platform_driver qdf2xxx_pinctrl_driver = { .driver = { .name = "qdf2xxx-pinctrl",