From patchwork Thu Jul 20 05:34:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 9853881 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 831C860392 for ; Thu, 20 Jul 2017 05:37:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70A0A20001 for ; Thu, 20 Jul 2017 05:37:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 64CFD28749; Thu, 20 Jul 2017 05:37:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E871820001 for ; Thu, 20 Jul 2017 05:37:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934071AbdGTFfY (ORCPT ); Thu, 20 Jul 2017 01:35:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39184 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934068AbdGTFfW (ORCPT ); Thu, 20 Jul 2017 01:35:22 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 03F2D611CF; Thu, 20 Jul 2017 05:35:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500528922; bh=zlr7kLADn3ebPasSl8ZyR/9injMHc3GP930bqCP/VRk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j5zpAYysJMpJSYVvgbf1sJXbMf3ogwE1kipc4Js9rUcpVaH/k1CHWm9GfVBTSs1DN ojR07jV+JdTDT5REdMiDs0hwmZcFc6t68+5y27BHa7wBHhtumFNQhy9to2jo0ujN+u laEecwo1UVekqd3X7nTCFts1Z34jdomTkDvBMtmM= Received: from varda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D6DD560FEB; Thu, 20 Jul 2017 05:35:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500528910; bh=zlr7kLADn3ebPasSl8ZyR/9injMHc3GP930bqCP/VRk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RJ2AsDHx4JA9bYASkdweYI095XnfuRWkCt5Ye+15cGubMmcRm7sdy2cjgg0nk56O0 iTar9r4DQKjUf/zCW5srocoHCIaupa11LeQcR2xkdedMTyud0aODgaWsDnkG4PGlSv L1beFOrisvcWFmjhbL723XxIFsAE4kuB6gpK3Xeo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D6DD560FEB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, svarbanov@mm-sol.com, kishon@ti.com, sboyd@codeaurora.org, vivek.gautam@codeaurora.org, fengguang.wu@intel.com, weiyongjun1@huawei.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Varadarajan Narayanan Subject: [PATCH v3 3/8] phy: qcom-qmp: Fix phy pipe clock name Date: Thu, 20 Jul 2017 11:04:35 +0530 Message-Id: <1500528880-25804-4-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500528880-25804-1-git-send-email-varada@codeaurora.org> References: <1500528880-25804-1-git-send-email-varada@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Presently, the phy pipe clock's name is assumed to be either usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the phy lane's number). However, this will not work if an SoC has more than one instance of the phy. Hence, instead of assuming the name of the clock, fetch it from the DT. Acked-by: Vivek Gautam Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-qmp.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 78ca628..97020ec 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -925,20 +925,13 @@ static int qcom_qmp_phy_clk_init(struct device *dev) * clk | +-------+ | +-----+ * +---------------+ */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id) +static int phy_pipe_clk_register(struct qcom_qmp *qmp, const char *clk_name) { - char name[24]; struct clk_fixed_rate *fixed; struct clk_init_data init = { }; - switch (qmp->cfg->type) { - case PHY_TYPE_USB3: - snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src"); - break; - case PHY_TYPE_PCIE: - snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id); - break; - default: + if ((qmp->cfg->type != PHY_TYPE_USB3) && + (qmp->cfg->type != PHY_TYPE_PCIE)) { /* not all phys register pipe clocks, so return success */ return 0; } @@ -947,7 +940,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id) if (!fixed) return -ENOMEM; - init.name = name; + init.name = clk_name; init.ops = &clk_fixed_rate_ops; /* controllers using QMP phys use 125MHz pipe clock interface */ @@ -1110,6 +1103,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { + const char *clk_name; + /* Create per-lane phy */ ret = qcom_qmp_phy_create(dev, child, id); if (ret) { @@ -1118,11 +1113,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return ret; } + ret = of_property_read_string(child, "clock-output-names", + &clk_name); + if (ret) { + dev_err(dev, + "failed to get clock-output-names for lane%d phy, %d\n", + id, ret); + return ret; + } + /* * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - ret = phy_pipe_clk_register(qmp, id); + ret = phy_pipe_clk_register(qmp, clk_name); if (ret) { dev_err(qmp->dev, "failed to register pipe clock source\n");