From patchwork Thu Jul 27 18:19:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 9867439 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 74FBC6038F for ; Thu, 27 Jul 2017 18:19:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66BB520952 for ; Thu, 27 Jul 2017 18:19:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B90E269DA; Thu, 27 Jul 2017 18:19:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC8C920952 for ; Thu, 27 Jul 2017 18:19:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751569AbdG0STe (ORCPT ); Thu, 27 Jul 2017 14:19:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57424 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751441AbdG0STc (ORCPT ); Thu, 27 Jul 2017 14:19:32 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DBE6160A06; Thu, 27 Jul 2017 18:19:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501179571; bh=ryQl2gx8W07/wC7eBpTk1//zsbkbEXvveneQBuvyKk0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JHKrfp0F5wREAwOZ6VXOS6brmccWzsUyJxrHfYZ1GEkbKESsdw/RQNrrWM0H/a8Bs FiQKkDXWRy7N8RfmiHPUHODlpTvciYiyfnKgkpvHlvXVncHZo6gpSXUiDHTzr7ZuLf AJS0U5XHXC9AUiILIEleDGvPMcYiZRPs8xFpI9MI= Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8117C6080C; Thu, 27 Jul 2017 18:19:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501179571; bh=ryQl2gx8W07/wC7eBpTk1//zsbkbEXvveneQBuvyKk0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JHKrfp0F5wREAwOZ6VXOS6brmccWzsUyJxrHfYZ1GEkbKESsdw/RQNrrWM0H/a8Bs FiQKkDXWRy7N8RfmiHPUHODlpTvciYiyfnKgkpvHlvXVncHZo6gpSXUiDHTzr7ZuLf AJS0U5XHXC9AUiILIEleDGvPMcYiZRPs8xFpI9MI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8117C6080C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: andy.gross@linaro.org, david.brown@linaro.org, Linus Walleij , Bjorn Andersson , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: timur@codeaurora.org Subject: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins Date: Thu, 27 Jul 2017 13:19:24 -0500 Message-Id: <1501179565-26466-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501179565-26466-1-git-send-email-timur@codeaurora.org> References: <1501179565-26466-1-git-send-email-timur@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To support sparse GPIO maps, pinctrl-msm client drivers can specify that a given GPIO has a pin count of zero. These GPIOs will be considered "hidden". Any attempt to claim the GPIO will fail, and they will not be listed in debugfs. During a kexec shutdown, machine_kexec_mask_interrupts() will attempt to disable all IRQs, even those that aren't enabled. This includes GPIOs that are unavailable (npins == 0), so add a check to the irq mask and unmask functions. Signed-off-by: Timur Tabi --- drivers/pinctrl/qcom/pinctrl-msm.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 273badd..6b4f353 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -494,6 +494,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, }; g = &pctrl->soc->groups[offset]; + + /* If the GPIO group has no pins, then don't show it. */ + if (!g->npins) + return; + ctl_reg = readl(pctrl->regs + g->ctl_reg); is_out = !!(ctl_reg & BIT(g->oe_bit)); @@ -503,7 +508,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); + seq_printf(s, " %s\n", pulls[pull]); } static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -511,23 +516,30 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned gpio = chip->base; unsigned i; - for (i = 0; i < chip->ngpio; i++, gpio++) { + for (i = 0; i < chip->ngpio; i++, gpio++) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } } #else #define msm_gpio_dbg_show NULL #endif +/* If the GPIO has no pins, then treat it as unavailable. */ +static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + return g->npins ? 0 : -ENODEV; +} + static struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, .set = msm_gpio_set, - .request = gpiochip_generic_request, + .request = msm_gpio_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, }; @@ -586,6 +598,10 @@ static void msm_gpio_irq_mask(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; + /* If there no pins, then this GPIO is unavailable */ + if (!g->npins) + return; + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); @@ -607,6 +623,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; + /* If there no pins, then this GPIO is unavailable */ + if (!g->npins) + return; + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg);