From patchwork Wed Sep 27 05:34:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vijay Viswanath X-Patchwork-Id: 9973047 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 74CD66037F for ; Wed, 27 Sep 2017 05:35:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 669E129098 for ; Wed, 27 Sep 2017 05:35:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B98B2909A; Wed, 27 Sep 2017 05:35:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 148C129098 for ; Wed, 27 Sep 2017 05:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751931AbdI0FfJ (ORCPT ); Wed, 27 Sep 2017 01:35:09 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52394 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751821AbdI0FfD (ORCPT ); Wed, 27 Sep 2017 01:35:03 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 11DAD60A36; Wed, 27 Sep 2017 05:35:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506490503; bh=cTcVG1DT0tuW3F3wEXF3Y4HGoBDmx2L8fbaLlF9y6N4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o0Jld9IMywqWX7UPDBwXi2Dbscp4IIbMNh4vR05ssCiFmZR81r/FTT4iqXM/qhS0w yMjrbdOpqRYB2f0BuZsxgh3wnA8/9GPQvc1dXjqIkapwSUU24E/BeVhbQOIe3IrlhX vDd6b6fzPfuhs4XJ9ckyEbbemhR1fl/c0vdAu+7c= Received: from hydcbspbld03.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vviswana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 125306029B; Wed, 27 Sep 2017 05:34:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506490502; bh=cTcVG1DT0tuW3F3wEXF3Y4HGoBDmx2L8fbaLlF9y6N4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h5EWdh8ShZx2HwRJe+J0s79SBVLv07ydXssx54alVnTSEN/SkSEGOo9coKCFWdIr/ AgpN4VQLlUAVI+WIqIP3aBS9K9Iv38zJ2r8r4TePqaov3VU51NCWyw9TAYSyvRAoA1 5AA7RgVvunVKxoRTgEG3pOVat2+iJmS6Edf5YG04= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 125306029B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vviswana@codeaurora.org From: Vijay Viswanath To: adrian.hunter@intel.com, ulf.hansson@linaro.org, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, asutoshd@codeaurora.org, stummala@codeaurora.org, riteshh@codeaurora.org, subhashj@codeaurora.org, Vijay Viswanath Subject: [PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq Date: Wed, 27 Sep 2017 11:04:40 +0530 Message-Id: <1506490483-46871-2-git-send-email-vviswana@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506490483-46871-1-git-send-email-vviswana@codeaurora.org> References: <1506490483-46871-1-git-send-email-vviswana@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Subhash Jadavani SDCC controller reset (SW_RST) during probe may trigger power irq if previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we enable the power irq interrupt in GIC (by registering the interrupt handler), we need to ensure that any pending power irq interrupt status is acknowledged otherwise power irq interrupt handler would be fired prematurely. Signed-off-by: Subhash Jadavani Signed-off-by: Vijay Viswanath Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 9d601dc..d636251 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1250,6 +1250,21 @@ static int sdhci_msm_probe(struct platform_device *pdev) CORE_VENDOR_SPEC_CAPABILITIES0); } + /* + * Power on reset state may trigger power irq if previous status of + * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq + * interrupt in GIC, any pending power irq interrupt should be + * acknowledged. Otherwise power irq interrupt handler would be + * fired prematurely. + */ + sdhci_msm_voltage_switch(host); + + /* + * Ensure that above writes are propogated before interrupt enablement + * in GIC. + */ + mb(); + /* Setup IRQ for handling power/voltage tasks with PMIC */ msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); if (msm_host->pwr_irq < 0) { @@ -1259,6 +1274,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto clk_disable; } + /* Enable pwr irq interrupts */ + writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK); + ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, sdhci_msm_pwr_irq, IRQF_ONESHOT, dev_name(&pdev->dev), host);