From patchwork Tue Oct 31 07:19:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Nischal X-Patchwork-Id: 10033653 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 60794602B9 for ; Tue, 31 Oct 2017 07:20:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5303A28901 for ; Tue, 31 Oct 2017 07:20:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4700428958; Tue, 31 Oct 2017 07:20:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2D9328999 for ; Tue, 31 Oct 2017 07:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753044AbdJaHUa (ORCPT ); Tue, 31 Oct 2017 03:20:30 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55256 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753030AbdJaHU3 (ORCPT ); Tue, 31 Oct 2017 03:20:29 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 68B37607BD; Tue, 31 Oct 2017 07:20:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509434428; bh=otvjkZdhb8tWgiL1wgOCXamczceYK9Miu3P+e9yI1F4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UYyeVC2fADodUn0cBaZhsNpbyrYu+1X18ysuGkboDh3Nz+vZSw0SLbxKt3c3+SrNo /89B/ZavQhXZ3KdQ29ReyjT/Q1c3DIHEvHHSs33NBEAuFqZRSoCeaxjsPOoVQIzssb 87J9HC8aHptx41/yk3xVN2+oadevTx54TvynTNWg= Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A6657606DC; Tue, 31 Oct 2017 07:20:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509434408; bh=otvjkZdhb8tWgiL1wgOCXamczceYK9Miu3P+e9yI1F4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EavkoRGmnyTgwGLiq9bUFve4mIJJtXHrroAmS0OEY2YPobhuWeKK1+AU1GSVGVt3G mePwvG3RFBHrzIE5H1HFkCc09PAuyw4O/UR9ZjWmw/KAdJJawqIUZP1YMU5z8AsFJl eRTkHm9pvusm28j1Iiz2DmGEhA5y0JIy3Kv9KCsc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A6657606DC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH 1/2] clk: qcom: clear hardware clock control bit of RCG Date: Tue, 31 Oct 2017 12:49:39 +0530 Message-Id: <1509434380-24372-2-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509434380-24372-1-git-send-email-anischal@codeaurora.org> References: <1509434380-24372-1-git-send-email-anischal@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For upcoming targets, the hardware clock control bit is set for most of root clocks which needs to be cleared for software to be able to control those root clocks. For older targets like MSM8996, this bit is reserved bit and having POR value as 0 so this patch will work for the older targets too. So update the configuration mask to take care of the same to clear hardware clock control bit. Signed-off-by: Amit Nischal --- drivers/clk/qcom/clk-rcg2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 1a0985a..ac9ce61 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -42,6 +42,7 @@ #define CFG_MODE_SHIFT 12 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) +#define CFG_HW_CLK_CTRL_MASK BIT(20) #define M_REG 0x8 #define N_REG 0xc @@ -276,7 +277,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) } mask = BIT(rcg->hid_width) - 1; - mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; + mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; cfg = f->pre_div << CFG_SRC_DIV_SHIFT; cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n))