From patchwork Tue Oct 31 07:19:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Nischal X-Patchwork-Id: 10033661 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A64E1602B9 for ; Tue, 31 Oct 2017 07:20:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 973172887E for ; Tue, 31 Oct 2017 07:20:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C3A328958; Tue, 31 Oct 2017 07:20:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3D182887E for ; Tue, 31 Oct 2017 07:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753083AbdJaHUb (ORCPT ); Tue, 31 Oct 2017 03:20:31 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55370 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753040AbdJaHU3 (ORCPT ); Tue, 31 Oct 2017 03:20:29 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 629376050D; Tue, 31 Oct 2017 07:20:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509434429; bh=2UXqNPqxflYhrH1ScfCs0dz9h3bJQvrult2hYoS0qdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AvvqLlE+NflRzsw82R4/XfNgHh9OZx9PE3TAUfU8e+jXQHTnQS4BQJh+DptbMnjoI 9eCvalFsJebI1XMEVcJg6qeMZ0GcZasIGVBhxPsS/sKnwiyEiXFxDDleZm11hH2Qbr MHo6tPZ8oQR7ppvPF62Bse/AaygyvDt4ifm4tcV4= Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CC1B26050D; Tue, 31 Oct 2017 07:20:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509434424; bh=2UXqNPqxflYhrH1ScfCs0dz9h3bJQvrult2hYoS0qdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hiva1x8FkN1RgmybG2qJhyWCcdnameS06Qh1hFo42Eak+1KZnm6yAHAp7UOO+LNbU jP8b6V7XNAgakHTeK08Of3OQZgGKPsfVxNfF9drUpfcoJAmJip8MC7FDmH2GGTOm8j rv6LizQClI7ydNKwMSQt79J3ccAML/Hhc5r1KYWU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CC1B26050D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH 2/2] clk: qcom: Modify RCG shared ops to support freq_tbl without XO entry Date: Tue, 31 Oct 2017 12:49:40 +0530 Message-Id: <1509434380-24372-3-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509434380-24372-1-git-send-email-anischal@codeaurora.org> References: <1509434380-24372-1-git-send-email-anischal@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There could be some clock sources where there is no entry corresponding XO in their frequency table, for such sources rcg2_shared_ops would wrongly configure the RCG registers during enable/disable, which leads to mismatch between the hardware and software rate so modify the shared ops to handle such cases. Signed-off-by: Amit Nischal --- drivers/clk/qcom/clk-rcg2.c | 79 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 70 insertions(+), 9 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index ac9ce61..8f7ca0c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -48,6 +48,14 @@ #define N_REG 0xc #define D_REG 0x10 +static struct freq_tbl cxo_f = { + .freq = 19200000, + .src = 0, + .pre_div = 1, + .m = 0, + .n = 0, +}; + enum freq_policy { FLOOR, CEIL, @@ -359,7 +367,7 @@ static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, }; EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); -static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +static int clk_rcg2_set_force_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const char *name = clk_hw_get_name(hw); @@ -373,22 +381,41 @@ static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) /* wait for RCG to turn ON */ for (count = 500; count > 0; count--) { - ret = clk_rcg2_is_enabled(hw); - if (ret) - break; + if (clk_rcg2_is_enabled(hw)) + return 0; + + /* Delay for 1usec and retry polling the status bit */ udelay(1); } if (!count) pr_err("%s: RCG did not turn on\n", name); + return -ETIMEDOUT; +} + +static int clk_rcg2_clear_force_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* clear force enable RCG */ + return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); +} + +static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +{ + int ret; + + ret = clk_rcg2_set_force_enable(hw); + if (ret) + return ret; + /* set clock rate */ ret = __clk_rcg2_set_rate(hw, rate, CEIL); if (ret) return ret; - /* clear force enable RCG */ - return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, - CMD_ROOT_EN, 0); + return clk_rcg2_clear_force_enable(hw); } static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, @@ -399,6 +426,11 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, /* cache the rate */ rcg->current_freq = rate; + /* + * Return if the RCG is currently disabled. This configuration + * update will happen as part of the RCG enable sequence. + */ + if (!__clk_is_enabled(hw->clk)) return 0; @@ -410,6 +442,12 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_rcg2 *rcg = to_clk_rcg2(hw); + if (!__clk_is_enabled(hw->clk)) { + if (!rcg->current_freq) + rcg->current_freq = cxo_f.freq; + return rcg->current_freq; + } + return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate); } @@ -417,6 +455,20 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); + if (rcg->current_freq == cxo_f.freq) { + clk_rcg2_set_force_enable(hw); + clk_rcg2_configure(rcg, &cxo_f); + clk_rcg2_clear_force_enable(hw); + + return 0; + } + + /* + * Switch from CXO to the stashed mux selection. The current + * parent has already been prepared and enabled at this point, + * and the CXO source is always on while application processor + * subsystem is online. Therefore, the RCG can safely be switched. + */ return clk_rcg2_shared_force_enable(hw, rcg->current_freq); } @@ -424,8 +476,17 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - /* switch to XO, which is the lowest entry in the freq table */ - clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0); + /* + * Park the RCG at a safe configuration - sourced off the CXO. + * Force enable and disable the RCG while configuring it to + * safeguard against any update signal coming from the downstream + * clock. The current parent is still prepared and enabled at this + * point, and the CXO source is always on while application processor + * subsystem is online. Therefore, the RCG can safely be switched. + */ + clk_rcg2_set_force_enable(hw); + clk_rcg2_configure(rcg, &cxo_f); + clk_rcg2_clear_force_enable(hw); } const struct clk_ops clk_rcg2_shared_ops = {