From patchwork Tue Nov 21 09:23:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manu Gautam X-Patchwork-Id: 10067781 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D887D6022E for ; Tue, 21 Nov 2017 09:23:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C866E28F43 for ; Tue, 21 Nov 2017 09:23:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD23928FCA; Tue, 21 Nov 2017 09:23:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 51CC428F43 for ; Tue, 21 Nov 2017 09:23:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751285AbdKUJXy (ORCPT ); Tue, 21 Nov 2017 04:23:54 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:40656 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751184AbdKUJXw (ORCPT ); Tue, 21 Nov 2017 04:23:52 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E55A4607F5; Tue, 21 Nov 2017 09:23:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511256231; bh=gdiJdescxIEuibWkVB4LNyIZ7uPQ8foUaVReAznvgoQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vvl565h5wxJfi/30aIopbPSrpqE8ucf8UriBWQkCSLhHDNdkEV7eSwkmX0nR4NXRl prcdNqttk4rDtrxFPYViqLWhPKdZEx0YfY6tbQjN0rEqLa5CnvNOChWzrbiUCAUfCD PY1x+i//W8zEVMojdHOJO+eDAe7zKBMaHZ/odSSQ= Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E0C776024A; Tue, 21 Nov 2017 09:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511256231; bh=gdiJdescxIEuibWkVB4LNyIZ7uPQ8foUaVReAznvgoQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vvl565h5wxJfi/30aIopbPSrpqE8ucf8UriBWQkCSLhHDNdkEV7eSwkmX0nR4NXRl prcdNqttk4rDtrxFPYViqLWhPKdZEx0YfY6tbQjN0rEqLa5CnvNOChWzrbiUCAUfCD PY1x+i//W8zEVMojdHOJO+eDAe7zKBMaHZ/odSSQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E0C776024A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Vivek Gautam , Manu Gautam , Varadarajan Narayanan , Krzysztof Kozlowski , Fengguang Wu , Wei Yongjun , linux-kernel@vger.kernel.org (open list:GENERIC PHY FRAMEWORK) Subject: [PATCH v3 01/16] phy: qcom-qmp: Fix phy pipe clock gating Date: Tue, 21 Nov 2017 14:53:11 +0530 Message-Id: <1511256206-1587-2-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511256206-1587-1-git-send-email-mgautam@codeaurora.org> References: <1511256206-1587-1-git-send-email-mgautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vivek Gautam Pipe clock comes out of the phy and is available as long as the phy is turned on. Clock controller fails to gate this clock after the phy is turned off and generates a warning. / # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on' [ 33.048585] ------------[ cut here ]------------ [ 33.052621] WARNING: CPU: 1 PID: 18 at ../drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xf0/0x108 [ 33.057384] Modules linked in: [ 33.066497] CPU: 1 PID: 18 Comm: kworker/1:0 Tainted: G W 4.12.0-rc7-00024-gfe926e34c36d-dirty #96 [ 33.069451] Hardware name: Qualcomm Technologies, Inc. DB820c (DT) ... [ 33.278565] [] clk_branch_wait+0xf0/0x108 [ 33.286375] [] clk_branch2_disable+0x28/0x34 [ 33.291761] [] clk_core_disable+0x5c/0x88 [ 33.297660] [] clk_core_disable_lock+0x20/0x34 [ 33.303129] [] clk_disable+0x1c/0x24 [ 33.309384] [] qcom_qmp_phy_poweroff+0x20/0x48 [ 33.314328] [] phy_power_off+0x80/0xdc [ 33.320492] [] dwc3_core_exit+0x94/0xa0 [ 33.325784] [] dwc3_suspend_common+0x50/0x60 [ 33.331080] [] dwc3_runtime_suspend+0x48/0x6c [ 33.336810] [] pm_generic_runtime_suspend+0x28/0x38 [ 33.342627] [] __rpm_callback+0x150/0x254 [ 33.349222] [] rpm_callback+0x24/0x78 [ 33.354604] [] rpm_suspend+0xe0/0x4e4 [ 33.359813] [] pm_runtime_work+0xdc/0xf0 [ 33.365028] [] process_one_work+0x12c/0x28c [ 33.370576] [] worker_thread+0x58/0x3b8 [ 33.376393] [] kthread+0x100/0x12c [ 33.381776] [] ret_from_fork+0x10/0x50 Fix this by enabling pipe clock at the end of phy_init(), and disabling it as the first thing in phy_exit(). Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Signed-off-by: Vivek Gautam Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index e17f035..76acaec 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -731,19 +731,10 @@ static int qcom_qmp_phy_poweron(struct phy *phy) /* turn on regulator supplies */ ret = regulator_bulk_enable(num, qmp->vregs); - if (ret) { + if (ret) dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - return ret; - } - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret); - regulator_bulk_disable(num, qmp->vregs); - return ret; - } - return 0; + return ret; } static int qcom_qmp_phy_poweroff(struct phy *phy) @@ -751,8 +742,6 @@ static int qcom_qmp_phy_poweroff(struct phy *phy) struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; - clk_disable_unprepare(qphy->pipe_clk); - regulator_bulk_disable(qmp->cfg->num_vregs, qmp->vregs); return 0; @@ -915,7 +904,14 @@ static int qcom_qmp_phy_init(struct phy *phy) goto err_pcs_ready; } - return ret; + /* phy is initialized; we can turn on the pipe clock now */ + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret); + goto err_pcs_ready; + } + + return 0; err_pcs_ready: if (cfg->has_lane_rst) @@ -936,6 +932,8 @@ static int qcom_qmp_phy_exit(struct phy *phy) const struct qmp_phy_cfg *cfg = qmp->cfg; int i = cfg->num_clks; + clk_disable_unprepare(qphy->pipe_clk); + /* PHY reset */ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);