From patchwork Sat Jan 13 01:05:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthikeyan Ramasubramanian X-Patchwork-Id: 10162063 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1B2E6602A7 for ; Sat, 13 Jan 2018 01:06:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C8E0289E8 for ; Sat, 13 Jan 2018 01:06:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 012E0289F8; Sat, 13 Jan 2018 01:06:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C969289E8 for ; Sat, 13 Jan 2018 01:06:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965465AbeAMBG1 (ORCPT ); Fri, 12 Jan 2018 20:06:27 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39032 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965397AbeAMBGW (ORCPT ); Fri, 12 Jan 2018 20:06:22 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 904D1607DC; Sat, 13 Jan 2018 01:06:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515805581; bh=pEEm8sDa1etVXWezCMBwMp2IpGvxsiWPTdHT0Jdh89s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sj7zjpyIkIt2IClRvj6V4IYQC/pe8e5mqjdgBJG6djEewNHVkn5PnEgqcXBmKkKqJ svtjg//WrEiGYz4KJRSwROdHtMT6erKWRfr2k5OIOxT8SKjSK5gXMuIRYt/1i+/vdn tlKX6Tvh1FzPwfVzCFPMKwOiynz+z/tvZYsia6fs= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kramasub@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 49AA460BF4; Sat, 13 Jan 2018 01:06:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515805576; bh=pEEm8sDa1etVXWezCMBwMp2IpGvxsiWPTdHT0Jdh89s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E92fdt1aDG5Z/N3ZSHm2jiETjXYEaoKBrzBLDpAEONPjFFUq32QZ7aOU4gLhRdAjj usd43aQASdBfskzdFll4fWme5eF8EX2l7GW+ur06ch5TJb1N0b6Vwb5RZyoszpnj+a RwQwpbxJx49egZDIZomdu4YjiZxedq/rzNx3/jLA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 49AA460BF4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=kramasub@codeaurora.org From: Karthikeyan Ramasubramanian To: corbet@lwn.net, andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wsa@the-dreams.de, gregkh@linuxfoundation.org Cc: Karthikeyan Ramasubramanian , linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, jslaby@suse.com, Girish Mahadevan Subject: [PATCH v2 6/7] dt-bindings: serial: Add bindings for GENI based UART Controller Date: Fri, 12 Jan 2018 18:05:46 -0700 Message-Id: <1515805547-22816-7-git-send-email-kramasub@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515805547-22816-1-git-send-email-kramasub@codeaurora.org> References: <1515805547-22816-1-git-send-email-kramasub@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree binding support for GENI based UART Controller in the QUP Wrapper. Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Girish Mahadevan --- .../devicetree/bindings/serial/qcom,geni-uart.txt | 29 ++++++++++++++++++++++ .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 13 ++++++++++ 2 files changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt new file mode 100644 index 0000000..e7b9e24 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt @@ -0,0 +1,29 @@ +Qualcomm Technologies Inc. GENI Serial Engine based UART Controller + +The Generic Interface (GENI) Serial Engine based UART controller supports +console use-cases and is supported only by GENI based Qualcomm Universal +Peripheral (QUP) cores. + +Required properties: +- compatible: should contain "qcom,geni-debug-uart". +- reg: Should contain UART register location and length. +- reg-names: Should contain "se-phys". +- interrupts: Should contain UART core interrupts. +- clock-names: Should contain "se-clk". +- clocks: clocks needed for UART, includes the core clock. +- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names + Should be "active" and "sleep" for the pin confuguration when core is active + or when entering sleep state. + +Example: +uart0: qcom,serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x7000>; + reg-names = "se-phys"; + interrupts = <0 355 0>; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; +}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt index 2ffbb3e..c307788 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt @@ -26,6 +26,7 @@ controller, spi controller, or some combination of aforementioned devices. See the following documentation for child node definitions: Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt +Documentation/devicetree/bindings/serial/qcom,geni-uart.txt Example: qup0: qcom,geniqup0@8c0000 { @@ -50,4 +51,16 @@ Example: #address-cells = <1>; #size-cells = <0>; }; + + uart0: qcom,serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x7000>; + reg-names = "se-phys"; + interrupts = <0 355 0>; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; + }; }