From patchwork Thu Jan 18 08:05:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vijay Viswanath X-Patchwork-Id: 10172427 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EBAA3601E7 for ; Thu, 18 Jan 2018 08:06:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD39120855 for ; Thu, 18 Jan 2018 08:06:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF1362094F; Thu, 18 Jan 2018 08:06:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5091420855 for ; Thu, 18 Jan 2018 08:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754007AbeARIGJ (ORCPT ); Thu, 18 Jan 2018 03:06:09 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:49182 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753918AbeARIGF (ORCPT ); Thu, 18 Jan 2018 03:06:05 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 41F2060A24; Thu, 18 Jan 2018 08:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516262765; bh=WkU13FTRJvSVxWog0pOZPQiSWe47QUEJuZqSzbDzkJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ja4M0m3vbfqdNxZGY3+8MCOcImbqOjSVmFOQU+SPGtU9bluXal9z6vINdY9nFQz+d ZYyhk24dQNAOtYd5uJvJ5wqvqaWdETFIccP17tkQB/NYc5gjR0VgUpAinFdpL41Ase g79zF7YwnDjfDpmX5TbkSTHuyAhON0SMK9h20hbo= Received: from hydcbspbld03.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vviswana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5601F6081E; Thu, 18 Jan 2018 08:06:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516262764; bh=WkU13FTRJvSVxWog0pOZPQiSWe47QUEJuZqSzbDzkJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oDLJByDxcydhH57vugo2hXmK8Lo4jxmR4f5MBmVB3ZH8ZFZ5oQOyTg8D59/Q7ZgrJ 2giWTQq6yTnHivdX8/s259FRmLtrb8RJLJg2mjEemmBxXhVXSOQU32MLjC/oIWUfnT 1qoC2kS66PP6i4tMFF+N4ieXY0rhfEL6KQenII5w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5601F6081E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vviswana@codeaurora.org From: Vijay Viswanath To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, asutoshd@codeaurora.org, stummala@codeaurora.org, venkatg@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, vviswana@codeaurora.org, Krishna Konda Subject: [PATCH RFC 2/2] mmc: sdhci-msm: support voltage pad switching Date: Thu, 18 Jan 2018 13:35:42 +0530 Message-Id: <1516262742-44326-3-git-send-email-vviswana@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516262742-44326-1-git-send-email-vviswana@codeaurora.org> References: <1516262742-44326-1-git-send-email-vviswana@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Krishna Konda The PADs for sdhc controller are dual-voltage that support 3v/1.8v. Those PADs have a control signal (io_pad_pwr_switch/mode18 ) that indicates whether the PAD works in 3v or 1.8v. SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset based on actual voltage used for IO lines. So when power irq is triggered for io high or io low, the driver should check the voltages supported and set the pad accordingly. Signed-off-by: Krishna Konda Signed-off-by: Venkat Gopalakrishnan Signed-off-by: Vijay Viswanath Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 5c23e92..f5728a8 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -78,6 +78,8 @@ #define CORE_HC_MCLK_SEL_DFLT (2 << 8) #define CORE_HC_MCLK_SEL_HS400 (3 << 8) #define CORE_HC_MCLK_SEL_MASK (3 << 8) +#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15) +#define CORE_IO_PAD_PWR_SWITCH (1 << 16) #define CORE_HC_SELECT_IN_EN BIT(18) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) @@ -1166,6 +1168,35 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) */ writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); + /* + * SDHC has core_mem and hc_mem device memory and these memory + * addresses do not fall within 1KB region. Hence, any update to + * core_mem address space would require an mb() to ensure this gets + * completed before its next update to registers within hc_mem. + */ + mb(); + /* + * We should unset IO PAD PWR switch only if the register write can + * set IO lines high and the regulator also switches to 3 V. + * Else, we should keep the IO PAD PWR switch set. + * This is applicable to certain targets where eMMC vccq supply is only + * 1.8V. In such targets, even during REQ_IO_HIGH, the IO PAD PWR + * switch must be kept set to reflect actual regulator voltage. This + * way, during initialization of controllers with only 1.8V, we will + * set the IO PAD bit without waiting for a REQ_IO_LOW. + */ + if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT)) + writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & + ~CORE_IO_PAD_PWR_SWITCH), host->ioaddr + + CORE_VENDOR_SPEC); + else if ((io_level & REQ_IO_LOW) || + (msm_host->caps_0 & CORE_1_8V_SUPPORT)) + writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | + CORE_IO_PAD_PWR_SWITCH), host->ioaddr + + CORE_VENDOR_SPEC); + /* Ensure that the IO PAD switches are updated before proceeding */ + mb(); + if (pwr_state) msm_host->curr_pwr_state = pwr_state; if (io_level) @@ -1518,6 +1549,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) } /* + * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH bit can + * be used as required later on. + */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | + CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr + + CORE_VENDOR_SPEC); + /* * Power on reset state may trigger power irq if previous status of * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq * interrupt in GIC, any pending power irq interrupt should be