From patchwork Mon Jan 22 13:03:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Ramana X-Patchwork-Id: 10178523 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F20C7602B7 for ; Mon, 22 Jan 2018 13:04:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 046C628334 for ; Mon, 22 Jan 2018 13:04:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 028182807B; Mon, 22 Jan 2018 13:04:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 94A5F2810E for ; Mon, 22 Jan 2018 13:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751099AbeAVNED (ORCPT ); Mon, 22 Jan 2018 08:04:03 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56434 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750970AbeAVNEC (ORCPT ); Mon, 22 Jan 2018 08:04:02 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 39F68607A4; Mon, 22 Jan 2018 13:04:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516626242; bh=+EM4JtulHA4A39GuPBR7zFc8iF3KI0UHadWF39e2p7w=; h=From:To:Cc:Subject:Date:From; b=j8keIzZSeLFuUiYJKJApjj9b7FWaFFAfMd6Dkor7mWrZQZuVy2vPVckExu76dw5H1 gMBgGUsxz0cu0UGerxDTvPfBpIOi4ggMDmClLaAcSz20wo4Bi5rc8mWNP4+Jn8Jaln TSso9CdYibR/4zW7I3DSrnFLHur+BR271A0/fd5Y= Received: from sramana-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sramana@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B0663601A1; Mon, 22 Jan 2018 13:03:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516626241; bh=+EM4JtulHA4A39GuPBR7zFc8iF3KI0UHadWF39e2p7w=; h=From:To:Cc:Subject:Date:From; b=DFUA4xXUYVUq9wq8Tn/iypQyu4qBaZ7NAJUftF6I8vsb9rn8UfqSEChcpKRC1baDT OoZ5pBo31xDyqaNsILU7x+Gu3c07/KQbG/07VKGdSNG0v9ZI2RuUAI26QnqMqOuVmc DM8mtstJldrdYfLCxiec8FoUgzt7FXf1qBKFlUcA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B0663601A1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sramana@codeaurora.org From: Srinivas Ramana To: bjorn.andersson@linaro.org, linus.walleij@linaro.org, timur@codeaurora.org, sboyd@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Ramana Subject: [PATCH] pinctrl: qcom: Add irq_enable callback for msm gpio Date: Mon, 22 Jan 2018 18:33:28 +0530 Message-Id: <1516626208-5655-1-git-send-email-sramana@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce the irq_enable callback which will be same as irq_unmask except that it will also clear the status bit before unmask. This will help in clearing any erroneous interrupts that would have got latched when the interrupt is not in use. There may be devices like UART which can use the same gpio line for data rx as well as a wakeup gpio when in suspend. The data that was flowing on the line may latch the interrupt and when we enable the interrupt before going to suspend, this would trigger the unexpected interrupt. This change helps clearing the interrupt so that these unexpected interrupts gets cleared. Signed-off-by: Srinivas Ramana --- drivers/pinctrl/qcom/pinctrl-msm.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 7a960590ecaa..de7c65c15f9e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -610,6 +610,36 @@ static void msm_gpio_irq_mask(struct irq_data *d) raw_spin_unlock_irqrestore(&pctrl->lock, flags); } +static void msm_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + /* + * clear the interrupt status bit before unmask to avoid + * any erroneous interrupts that would have got latched + * when the intterupt is not in use. + */ + val = readl(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + set_bit(d->hwirq, pctrl->enabled_irqs); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + static void msm_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -767,6 +797,7 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) static struct irq_chip msm_gpio_irq_chip = { .name = "msmgpio", + .irq_enable = msm_gpio_irq_enable, .irq_mask = msm_gpio_irq_mask, .irq_unmask = msm_gpio_irq_unmask, .irq_ack = msm_gpio_irq_ack,